EE141_sp03_final

EE141_sp03_final - University of California College of...

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EECS 141: SPRING 03—FINAL 1 University of California College of Engineering Department of Electrical Engineering and Computer Science Jan M. Rabaey TuTh 9:30-11am EECS 141: SPRING 03—FINAL NAME Last First SID Total (75) Problem 2 (15): Problem 1 (10): Problem 3 (14): Problem 4 (18): For all problems, you can assume the following transistor parameters NMOS: V Tn = 0.4V, k n ’ = 115μA/V 2 , V DSAT = 0.6V, λ = 0, γ = 0.4V 1/2 , 2 Φ F = -0.6V PMOS: V Tp = -0.4V, k p ’ = -30μA/V 2 , V DSAT = -1V, λ = 0, γ = -0.4V 1/2 , 2 Φ F = 0.6V (unless otherwise mentioned): Problem 5 (18):
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EECS 141: SPRING 03—FINAL 2 Problem 1: Timing and Clocking (10 pts) In order to boost profits, Intel has decided that their next-generation microprocessor has to have ultimate performance. To achieve the desired performance, 16 processors are integrated on the same die (the chip is hence called seidecium – for obvious reasons). The designer of the clocking architecture has come up with the strategy shown in the Figure below. A single clock signal is distributed over the complete chip. Three levels of buffer- ing are used as shown by the black boxes in the Figure. a) Determine the maximum skew between the different processor modules. (4 pts) P 1 P 16 P 2 10 5 1 3 1 FIG. 1 Seidecium processor clock distribution network. The numbers annotated on the figure indicate the lengths of the wiring segments (in cm). Important parameters: t pbuffer (level 1,2,3) = 0.1ns r wire 0.1 k () cm = c 0.1 pF = max skew:
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EECS 141: SPRING 03—FINAL 3 b) The goal of the designers is to reach a 4 GHz clock speed. Determine the maxi- mum delay of the logical function blocks given that 20% of the clock period is due to the delay of registers. Also, note that the maximum internal skew within a pro- cessor module equals 20 ps. (3 pts) c) The Intel designers forgot to account for one thing though. Due to the parameters variations over the die, it is observed that the delay of the clock buffers can vary over 25% (in both positive and negative directions). Determine the worst-case clock speed due to these variations. (3 pts) t logic (max)= f clock (min)=
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EECS 141: SPRING 03—FINAL 4 Problem 2: Interconnect (15 pts) a) A driver-receiver pair in CMOS technology is shown in Figure 2.
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EE141_sp03_final - University of California College of...

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