MP SoC Design - Scheduling and Timing Analysis of HW/SW...

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Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design Youngchul Cho*, Ganghee Lee*, Sungjoo Yoo**, Kiyoung Choi*, and Nacer-Eddine Zergainoh** *Design Automation Lab. Seoul National University, Korea **SLS Group TIMA Lab., France ABSTRACT On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip communication network, communication interfaces of processor/IP/memory, on-chip memory, etc.). For an efficient exploration of its design space, we need fast scheduling and timing analysis. In this work, we tackle two problems (one for SW and the other for HW) in on-chip communication design. One is to incorporate the dynamic behavior of SW (interrupt processing and context switching) into on-chip communication scheduling. The other is to reduce on-chip data storage required for on-chip communication, by sharing physical communication buffers with different communication transactions. To solve the problems, we present both ILP (integer linear programming) formulation and heuristic algorithm, which enable the designer to perform efficient on- chip communication scheduling and obtain accurate timing information. Experimental results show the effectiveness of our work. 1 Introduction In multiprocessor system on chip (MP-SoC) design, on-chip communication is one of crucial design steps. By on-chip communication design, we mean both (1) mapping and scheduling of on-chip communication and (2) the design of both the HW part of communication architecture (i.e. communication network, communication interfaces) and the SW part (i.e. operating system, device drivers, interrupt service routines (ISRs), etc.). We call the two parts HW communication architecture and SW communication architecture, respectively. In our work, we tackle two problems (one for SW and the other for HW) in on-chip communication design. First, we present a method of incorporating, into on-chip communication scheduling, the dynamic behavior of SW (interrupt processing and context switching) related to on- chip communication. Second, to reduce on-chip data storage (in our terms, physical communication buffer) required for on-chip communication, we tackle a problem of sharing physical communication buffers with different communications in on-chip communication scheduling. On-chip communication design considering both SW and HW communication architectures Most of previous on-chip communication design methods focus on HW communication architecture design, such as bus topology design, determining bus priorities, and DMA size optimization [3][4][6][7]. A few studies consider the SW communication architecture in on-chip communication design [5][8]. In [5], a method of SW architecture implementation is presented. In [8], device driver runtime (which depends statically on the size of transferred data) is considered to estimate on-chip communication runtime. However, the behavior of SW communication architecture is dynamic. The dynamism includes interrupt processing, context switching, etc. Since
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This note was uploaded on 03/07/2010 for the course ECE 1212 taught by Professor Jame during the Spring '09 term at Punjab Engineering College.

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MP SoC Design - Scheduling and Timing Analysis of HW/SW...

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