LAB1-248 - high. Since high to low is just a half cycle the...

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NITHEJ PILLI ECEN 248 – 505 Lab Report #1 Vinay Karkala September 23, 2009
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Objectives: The first part of the lab reinforced the basics of the bread board along with using the various logic gates in simple circuits. The second part of the lab focused on inverters and specifically on an interesting inverter characteristic – time delay. A Y (Volts) Y (H/L) L 4.44 H H 0.13 L Table 1.1: Truth Table for Inverter A B And2 (V) And2 (H/L) Or2 (V) Or2 (H/L) L L 0.09 L 0.10 L L H 0.09 L 4.45 H H L 0.09 L 4.45 H H H 4.44 H 4.45 H A B Nand2(V) Nand2(H/L ) Nor2 (V) Nor2(H/L ) Xor2(V) Xor2(H/L ) L L 4.44 H 4.45 H 0.17 L L H 4.44 H 0.11 L 4.44 H H L 4.44 H 0.11 L 4.44 H H H 0.15 L 0.11 L 0.18 L Table 1.3: a) Range of input values: (i) Output = 1 for input ranging from (0, .9) (ii) Output = 0 for input ranging from (1, 2.3) b) (i) A single-stage delay is the time difference of a single inverter from one high to another
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Unformatted text preview: high. Since high to low is just a half cycle the period of oscillation from high to high has to be multiplied by 2. Therefore, T = 2 * Dinv giving us Dinv = T/2. (ii) if Dinv = 10ns, n = 21, f = 1/T, T = 2 * Dinv. Therefore f = 2.38 MHz c) The Signals at P, Q, R, S are part of a larger system which we have already proved as periodic because of its oscillation, therefore these signals have to be periodic too. The time period it takes for one gate to switch its output from H to H or L to L is just the overall time period which we have measured to be 58 ns. Signals P & R have the opposite value of A whereas signals Q & S retain the same value....
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LAB1-248 - high. Since high to low is just a half cycle the...

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