pre-lab - Lab 6 (Sections 500 and 501) Prelab: Introduction...

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Unformatted text preview: Lab 6 (Sections 500 and 501) Prelab: Introduction to Verilog Name: Nithej Pilli Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work Nithej Pilli 1 Objective The main objective of this lab is to give hands on experience with Verilog HDL and the Xilinx ISE. For this lab you are expected to know some basic Verilog programming and understand the Xilinx ISE. 2 Introduction Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit (IC) designers. The other one is VHDL. HDLs allow the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology-independent, easy to debug, and are usually more readable than schematics, particularly for large circuits. Verilog can be used to describe designs at four levels of abstraction: 1. Algorithmic level (much like C code with if-else, while, case and loop statements). 2. Register transfer level (RTL uses registers connected by Boolean equations). 3. Gate level (interconnected AND, NOR etc.). 1 Computer Architecture and Design, PreLab 6 2 4. Switch level (the switches are MOS transistors inside gates). The language also defines constructs that can be used to control the input and output of simulation. More recently Verilog is used as an input for synthesis programs which will generate a gate-level description (a netlist) for the circuit. The netlist can then be loaded on to a chip called FPGA (Field Programmable Gate Arrays), which is a generic chip on which any functionality can be programmed and re-programmed when required. 3 Questions 1. What is the difference between Structural and Behavioral programming style? Give an example for each style. Behavioral: describe what a module does assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; Structural: describe how a module is built from simpler modules ex. Functions defining the primitive gates.. module and(a,b,c) module or(a,b,c) Instantiating and calling the functions - define gates Memory Element and andgate(h,g,u) 2. Design an JK Flip-Flop comprising of just NAND gates. Give the Truth Table for the circuit. Write a structural Verilog program for the JK Flip-Flop JKQ 000 010 101 111 module JKFF(J,K,Clk,Q,Q_bar) inputs J,K,Clk outputs Q,Q_bar wire w1,w2 nand n1 (w1,J,Clk,Q_bar) nand n2 (w2,K,Clk,Q) nand n3 (Q,Q_bar,w1) nand n4 (Q_bar,Q,w2) endmodule Computer Architecture and Design, PreLab 6 3 3. Develop a testbench for 2-to-1 MUX that verifies the structural model. The testbench will have no ports. Exhaustively simulate the circuit and print the output demonstrating that the model is correct. Text output can be generated using the $monitor and $display tasks. module JK_test() reg j,k; wire q; JKFF jk1 (j,k,q); initial begin j=0; k=0; #10 if (q!=0) $display("00 failed "); k=1; #10 if (q!=0) $display("01 failed "); j=1; #10 if (q!=1) $display("11 failed "); k=0; #10 if (q!=1) $display("10 failed "); endmodule 4. Multiplexor Design a 2-to-1 MUX Circuit, that multiplexes two input signals to a single output based on the select signal. Fig. 1: Multiplexor (a) Give the truth table for the circuit: i0 i1 sel out -----------------001 0 000 0 011 1 010 0 101 0 100 1 111 1 110 1 Computer Architecture and Design, PreLab 6 4 (b) Design the Optimal Circuit design using the basic gates (not to be submitted). (c) Write a structural Verilog model for the 2-to-1 MUX: module mux(a,b,select,y) inputs a,b,select; outputs y; wire select_bar,w1,w2; not (select_bar, select); and (w1, select_bar, a); and(w2, select, b); or (y, w1, w2); endmodule (d) Develop a testbench for 2-to-1 MUX that verifies the structural model. module mux_test() reg a, b, select; wire y; mux m1 (a,b,select,y); initial begin a=0; b=0; select=0; #10 if (y!=0) $display("000 failed "); a=1; #10 if (y!=1) $display("100 failed "); b=1; #10 if (y!=1) $display("110 failed "); select=1; #10 if (y!=1) $display("111 failed "); a=0; b=0; #10 if (y!=0) $display("001 failed "); a=1; #10 if (y!=0) $display("101 failed "); a=0; b=1; #10 if (y!=1) $display("011 failed "); select=0; #10 if (y!=0) $display("010 failed "); endmodule ...
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