FPLDs - Field Programmable Logic Devices (FPLDs) Overview...

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ECE 3450 M. A. Jupina, VU, 2006 Overview of Digital Logic Technologies FPLD Technologies Altera UP-1 Development Board Hardware Description Languages Quartus II Software and Tutorial Field Programmable Logic Devices (FPLDs)
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ECE 3450 M. A. Jupina, VU, 2006 Some Key Lecture Objectives A discussion of how digital logic circuits can be implemented through various technologies (Discrete vs PLD vs ASIC vs Full Custom). Understand how FPLD technology is implemented by briefly looking at CPLD and FPGA architectures. Understand the advantages of FPLD technology. An overview of the Altera UP-1 board and the Quartus II software. Course projects will use the Altera UP-1 board as a platform to implement complicated digital systems. With the Quartus II software, you will use a system design approach to create your designs. A brief (very brief) discussion of VHDL and the future of VHDL-AMS and mixed signal ICs. References : 1. Fundamentals of Digital Logic, Sections 2.9, 2.10, 3.5 – 3.7, and Appendices A-E. 1. Document files at the course web site
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ECE 3450 M. A. Jupina, VU, 2006 Digital Logic Technologies Full Custom Standard Logic Progammable Logic (FPLDs) ASICs Digital Logic TTL 74xx CMOS 4xxx PLDs FPGAs Gate Arrays Microprocessor & RAM Standard Cell CPLDs
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ECE 3450 M. A. Jupina, VU, 2006 A 7400-Series Chip Dual-inline package Structure of 7404 chip V DD Gnd
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ECE 3450 M. A. Jupina, VU, 2006 V D D x 1 x 2 x 3 f 7404 7408 7432 Discrete Implementation Example 1 2 2 3 f = x x + x x
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ECE 3450 M. A. Jupina, VU, 2006 General Structure of a PLA f 1 AND plane OR plane Input buffers inverters and P 1 P k f m x 1 x 2 x n x 1 x 1 x n x n
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ECE 3450 M. A. Jupina, VU, 2006 An Example of a PLA f 1 P 1 P 2 f 2 x 1 x 2 x 3 OR plane AND plane P 3 P 4 1 1 2 1 3 1 2 3 2 1 2 1 2 3 1 3 f x x x x x x x f x x x x x x x = + + = + +
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ECE 3450 M. A. Jupina, VU, 2006 An Example of a PAL f 1 P 1 P 2 f 2 x 1 x 2 x 3 AND plane P 3 P 4 1 1 2 3 1 2 3 2 1 2 1 2 3 f x x x x x x f x x x x x = + = +
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ECE 3450 M. A. Jupina, VU, 2006 Structure of a CPLD PAL-like block I/O block PAL-like block PAL-like block PAL-like block Interconnection wires
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ECE 3450 M. A. Jupina, VU, 2006 A Section of a CPLD D Q D Q D Q PAL-like block (details not shown) PAL-like block
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ECE 3450 M. A. Jupina, VU, 2006 Structure of a FPGA
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ECE 3450 M. A. Jupina, VU, 2006 Logic Block Example A two-input lookup table (a) Circuit for a two-input LUT x 1 x 2 f 0/1 0/1 0/1 0/1 0 0 1 1 0 1 0 1 1 0 0 1 x 1 x 2 (b) f 1 x 1 x 2 x 1 x 2 + = (c) Storage cell contents in the LUT x 1 x 2 1 0 0 1 f 1 f 1 Out D Q Clock Select Flip-flop In 1 In 2 In 3 LUT Complete Logic Block
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ECE 3450 M. A. Jupina, VU, 2006 A Sea-of-Gates Gate Array
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ECE 3450 M. A. Jupina, VU, 2006 An Example of a Logic Function in a Gate Array f 1 x 1 x 3 x 2 1 2 3 1 3 f = x x + x x
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ECE 3450 M. A. Jupina, VU, 2006 A Simplified Floor Plan of a Standard Cells Based Design
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ECE 3450 M. A. Jupina, VU, 2006 Standard Cell Structure
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FPLDs - Field Programmable Logic Devices (FPLDs) Overview...

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