MOS_Digital_Logic_Technology

MOS_Digital_Logic_Technology - Metal-Oxide-Semiconductor...

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ECE 3450 M. A. Jupina, VU, 2006 Metal-Oxide-Semiconductor Field-Effect Transistor Digital Logic Technology CMOS Fabrication MOS Device Structure and Operation NMOS Circuits CMOS Circuits BiCMOS Circuits
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ECE 3450 M. A. Jupina, VU, 2006 Some Key Lecture Objectives A basic understanding of the layout and structure of MOS devices and circuits A basic understanding of the electrical operation of MOSFETs How logic functions can be synthesized in CMOS and why CMOS is the dominate digital technology today A more fundamental understanding of power dissipation in MOS technologies When should BiCMOS technology be used and why Reference : Fundamentals of Digital Logic, Chapter 3.
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ECE 3450 M. A. Jupina, VU, 2006 CMOS Fabrication Processes IC built on silicon substrate: some structures diffused into substrate; other structures built on top of substrate. Substrate regions are doped with n-type and p- type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum/copper (metal). Silicon dioxide (SiO 2 ) is an insulator.
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ECE 3450 M. A. Jupina, VU, 2006 Simple Cross Section of a MOS Integrated Circuit substrate n+ n+ p substrate metal1 poly SiO 2 metal2 metal3 transistor via
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ECE 3450 M. A. Jupina, VU, 2006 Example: Cross Section of Intel 0.25 Micron Process
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ECE 3450 M. A. Jupina, VU, 2006 CMOS Fabrication Processing Steps First place tubs or wells to provide properly- doped substrate for nmos and pmos transistors: p-tub n-tub substrate
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ECE 3450 M. A. Jupina, VU, 2006 Processing Steps, Cont’d. Pattern polysilicon before diffusion regions: p-tub n-tub poly poly gate oxide
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ECE 3450 M. A. Jupina, VU, 2006 Processing Steps, Cont’d Add diffusions (self-aligned source and drain) p-tub n-tub poly poly n+ n+ p+ p+
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ECE 3450 M. A. Jupina, VU, 2006 Processing Steps, Cont’d Start adding metal layers: p-tub n-tub poly poly n+ n+ p+ p+ metal 1 metal 1 vias
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ECE 3450 M. A. Jupina, VU, 2006 Processing Steps, Cont’d Add other metal interconnect layers: p-tub n-tub poly poly n+ n+ p+ p+ metal 1 metal 1 vias metal 2
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ECE 3450 M. A. Jupina, VU, 2006 MOS Transistor Layout NMOS FET: PMOS FET: w L w L
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ECE 3450 M. A. Jupina, VU, 2006 NMOS Transistor Structure nmos transistor:
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ECE 3450 M. A. Jupina, VU, 2006 + (a) Small transistor L W 1 L W 2 (b) Larger transistor Transistor Sizes
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ECE 3450 M. A. Jupina, VU, 2006 ++++++ ++++ ++++++ +++ ++++++ ++++++ ++++++ ++++++ +++++++++ +++++++++ +++++++++++ +++++++++++ Drain (type n) Source (type n) Substrate (type p) SiO 2 When V GS < V T , the transistor is off V S 0 V = V G 0 V = V D ++++++ ++++++ ++++++ ++++++ 0 D I = NMOS Transistor When Turned Off
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ECE 3450 M. A. Jupina, VU, 2006 ++++++ ++++ +++ ++++++ ++++++ ++++++ +++++++++ ++++++++++ +++++++++++ +++++++++++++++++ Channel (type n) SiO 2 V DD When V GS > V T , the transistor is on ++ +++++++ V D V G 5 V = V S 0 V = 0 D I NMOS Transistor When Turned On
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ECE 3450 M. A. Jupina, VU, 2006
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MOS_Digital_Logic_Technology - Metal-Oxide-Semiconductor...

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