Ch5-new - EE 306 Introduction to Computing Chapter 5: The...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Ramesh Yerraballi 5-1 EE 306 Introduction to Computing Chapter 5: The LC-3 Instruction Set Architecture Ramesh Yerraballi 5-2 ISA Overview Memory Address space Addressability: Word or Byte Registers Number Type Instructions Operations Data Types Addressing Modes
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Ramesh Yerraballi 5-3 LC-3 Memory Organization addressability word (16 bits/location) address space 2 16 locations = 64k 2 9 words/page = 512 2 7 pages =128 page location in page [8:0] [15:9] Address [16:0] Ramesh Yerraballi 5-4 General Purpose Registers (GPRs) Registers Special “memory” that is “inside” the CPU Very fast access: 1 clock cycle. General Purpose Registers: addressable by an instruction (visible to the user). Other registers may not be accessible (not architectured) LC-3 8 general purpose registers: R0,R1,. ..,R7 • a register can hold any 16 bit pattern - i.e. data or addresses 1111 1111 1111 1000 Register 7 (R7) 1111 1111 1111 1010 Register 6 (R6) 1111 1111 1111 1100 Register 5 (R5) 1111 1111 1111 1110 Register 4 (R4) 0000 0000 0000 0111 Register 3 (R3) 0000 0000 0000 0101 Register 2 (R2) 0000 0000 0000 0011 Register 1 (R1) 0000 0000 0000 0001 Register 0 (R0) 1111 1111 1111 1000 Register 7 (R7) 1111 1111 1111 1010 Register 6 (R6) 1111 1111 1111 1100 Register 5 (R5) 1111 1111 1111 1110 Register 4 (R4) 0000 0000 0000 0111 Register 3 (R3) 0000 0000 0000 0100 Register 2 (R2) 0000 0000 0000 0011 Register 1 (R1) 0000 0000 0000 0001 Register 0 (R0) 1 0 0 1 R1 0 2 0 3 0 4 0 5 0 6 0 7 R0 0 8 0 9 1 1 0 R2 0 1 1 1 1 2 0 1 3 0 1 4 ADD 0 1 5
Background image of page 2
3 Ramesh Yerraballi 5-5 Instructions Two main parts Opcode: specifies what the instruction does. Operand(s): what the instruction acts on Instruction sets can be complex or simple LC-3 4-bit opcode => 16 instructions up to two sources and one destination Ramesh Yerraballi 5-6 Operations Operate Manipulate data directly • ADD(0x1), AND(0x5), NOT(0x9) Data Movement Move data between memory and registers (CPU) • LD(0x2), LDI(0xA), LDR(0x6), LEA(0xE), ST(0x3), STI(0xB), STR(0x7) Control Change the sequence of instruction execution • BR(0x0), JMP/JSR(0xC/0x4), JSRR(0x4), RET(0xC), RTI(0x8), TRAP(0xF)
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 Ramesh Yerraballi 5-7 Data Types What data types are supported by the computer instructions? Eg. integer, floating point, BCD, character . .. LC-3: only 2's complement integers bit strings and addresses are not data types Ramesh Yerraballi 5-8 Condition Codes 3 single-bit registers (set to 1 or cleared to 0) N: value written was negative Z: value written was zero P: value written was positive Instructions that modify (set or clear) them: ADD, AND, LD, LDI, LDR, LEA, NOT Affected each time any register is written Condition codes are read by conditional branch instructions
Background image of page 4
5 Ramesh Yerraballi 5-9 Addressing Modes Where is the operand? The addressing modes provide multiple mechanisms for the
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/10/2010 for the course EE 306 taught by Professor Ambler during the Spring '07 term at University of Texas at Austin.

Page1 / 18

Ch5-new - EE 306 Introduction to Computing Chapter 5: The...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online