Lecture-01 - EEE 525: VLSI Design, L-01 Introduction Spring...

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Unformatted text preview: EEE 525: VLSI Design, L-01 Introduction Spring 2010, ASU Yu (Kevin) Cao, yu.cao@asu.edu, GWC 336 Highlight Course orientation – Objective, textbook, assignments, and grading policy Challenges and design trend and design trend – Grand challenges: power, variability, reliability, interconnection – Design paradigm shift Reading: Chapter 1 Handout: Syllabus, Schedule, and Qualify Exam EEE525, ASU, Y. Cao Lecture 01 -2- 1 Highlight Course orientation – Objective, textbook, assignments, and grading policy Challenges and design trend and design trend – Grand challenges: power, variability, reliability, interconnection – Design paradigm shift Reading: Chapter 1 Handout: Syllabus, Schedule, and Qualify Exam EEE525, ASU, Y. Cao Lecture 01 -3- Basic Information Instructor: Y. Kevin Cao, GWC 336 – Office hour: W: 1pm-3pm; E-mail: yu.cao@asu.edu TA: Hyunjun Kim (hjkim12@asu.edu) – MW: 12:00pm-6:00pm; TTh: 11:00am-3:00pm Textbook: – CMOS VLSI Design: A Circuits and Systems Perspective, by Neil H. E. Weste and David Harris Other references: – Design of High-Performance Microprocessor Circuits, Edited by A. Chandrakasan et al Chandrakasan, et al. – Nano-CMOS Circuit and Physical Design, by B. P. Wong, A. Mittal, Y. Cao, and G. Starr – Low Power Design Essentials, by J. Rabaey Lab at GWC 273, with TA available Lectures etc. are available at http://my.asu.edu EEE525, ASU, Y. Cao Lecture 01 -4- 2 What Will You Learn VLSI design knowledge that is both fundamental and practical, in the context of key design principles – Focus: VLSI circuit and system design for advanced CMOS technology Pre-requisite: basic understanding of CMOS and digital circuits – Online students are required to have their own access to design tools – Evaluate yourself by taking Qualify Exam! Content: Fundamental CMOS, speed, power, reliability Practical ALU, memory, datapath, clock, power, I/O, CAD Further study: computer architecture, CAD, and analog design EEE525, ASU, Y. Cao Lecture 01 -5- Class Schedule EEE525, ASU, Y. Cao Lecture 01 -6- 3 Assignments Homework (15%): exercise your learning – Totally five: three before Midterm and two after it – Part of them will be software labs Project : design and optimization of a datapath circuit – Phase I (15%): schematic design with Spectre/SPICE – Phase II (15%): layout, extraction, and optimization – Two people per group, with balanced contribution – The load will be adjusted for online students – Grade is based on the ranking of design quality: speed, power, is based on the ranking of design quality: speed power area, layout, and report Examination: evaluate your knowledge – One mid-term (25%): design fundamentals – Final (30%): majority of the final is from the second half EEE525, ASU, Y. Cao Lecture 01 -7- Grading Policy Letter grade depends on the relative distribution, with + and – (μ: average; σ: standard deviation) – A+: top 10% – A: > μ + 0.5·σ – A-: > μ – B+: > μ - 0.5·σ – B: > μ – σ – B-: > μ – 1.5σ – C: > μ - 2·σ – D: else HW (15%), Project (30%), Midterm (25%), Final (30%) EEE525, ASU, Y. Cao Lecture 01 -8- 4 Highlight Course orientation – Objective, textbook, assignments, and grading policy Challenges and design trend and design trend – Grand challenges: power, variability, reliability, interconnection – Design paradigm shift Reading: Chapter 1 Handout: Syllabus, Schedule, and Qualify Exam EEE525, ASU, Y. Cao Lecture 01 -9- Technology Scaling 1947 2002 (90nm node) 2015? 15nm ???? 50nm “Research and technology development … in the length scale of approximately 1-100 nanometer range.” Dr. Mike Roco, National Science and Technology Council, February 2000 EEE525, ASU, Y. Cao Lecture 01 - 10 - 5 Grand Success Number of Transistors 10000 1000 100 10 1 1m 100 10 1 100nm 0 .1 1m Million Clock Frequency GHz 10-4 10-5 10nm 10-6 10-7 100nm 10-8 10-9 1m 100nm 10nm 10nm Cost per Transistor Dollar EEE525, ASU, Y. Cao Lecture 01 - 11 - Recent Slowing Down Semiconductor Revenue/Year ($B) 10 10 10 10 10 10 10 3 10 1 2 Revenue ($B) 10 0 Cost/Transistor (normalized) a 1 0 -1 10 -1 -2 Cost/Unit Data: ISSCC ‘07 1960 1970 1980 1990 2000 10 2010 -2 -3 1950 PrePre-Si Silicon Post-Si Post- EEE525, ASU, Y. Cao Lecture 01 - 12 - 6 Roadblock 0: Scalability Wavelength in lithography CMOS Technology e- mean free path Silicon lattice Node 365nm 1μm Leff 12nm 2nm Tox Tox 1nm 0.54nm 157nm 32nm 100nm Wavelength Gate length 10nm 1989 1993 1997 2001 2005 2009 Leff Many secondary effects are now critical: leakage, variations, reliability, manufacturability, ... EEE525, ASU, Y. Cao [S. Thompson, Univ. of Florida] Lecture 01 - 13 - Roadblock 1: Power Energy per switching reduces with scaling But, total chip power increases Constrains system E/transistor (fJ) Power (W) integration and chip performance 102 103 102 101 101 100 100 10-1 -2 10-1 Cload Switching Vdd2 Increase the cost Limits the battery time of handheld electronics EEE525, ASU, Y. Cao 10-3 10-2 10-4 Leakage 100nm 100nm 1m 10nm 10nm Technology node Technology node 1m 10m Source: Intel Lecture 01 - 14 - 7 Roadblock 2: Variability Process variations: 50% 40% Leff wire (w, h, ) (w Leff, Vth, Tox, etc. 3/mean 30% 20% 10% 0% 250 Environmental: 65 Vth Tox 180 130 90 Vdd, Temperature, workload, crosstalk noise, etc. Technology node (nm) Source: IBM and ITRS Variations can be parametric or non-parametric Lecture 01 - 15 - EEE525, ASU, Y. Cao SRAM: Dominating Transistors 6T SRAM: still the best Logic SRAM candidate High speed operation Hi Increased # of transistor counts (>50%) – Itanium 2: 144M/220M Larger on-chip area Itanium 2 Chip Chi Dominating chip leakage and a major source of total power consumption (>20%) The most vulnerable to process variations EEE525, ASU, Y. Cao Lecture 01 - 16 - 8 Roadblock 3: Reliability Scaling reduces signal-to-noise ratio (SNR) New degradation mechanisms are emerging Errors can and will happen everywhere can and will happen everywhere 3 HCI limited Vdd (V) 2 Scaling trend NBTI limited li 1 2 3 4 5 Tox (nm) Source: VLSI Tech. 1999 EEE525, ASU, Y. Cao Lecture 01 - 17 - Roadblock 4: Interconnection Density against everything for a wire: speed, bandwidth, resistivity, manufacturability, reliability What’s after Cu??? CMOS Challenges • Power dissipation, delivery and density • Random dopant fluctuations impact – Need a dense, fast access memory cell to go with logic – What could replace the SRAM memory cell • Interconnect – Density – bandwidth and latency ratio 12 I. Young 12/12/03 I. Young, at C2S2 Workshop, Dec. 2003 EEE525, ASU, Y. Cao Lecture 01 - 18 - 9 Evolution Proceeds with Extinctions EEE525, ASU, Y. Cao Lecture 01 - 19 - So does the Electronics… How to avoid the mass extinctions? “It is not the strongest of the species who survive, not the most intelligent, but those who are the most adaptive to change” – Charles Darwin EEE525, ASU, Y. Cao Lecture 01 - 20 - 10 Design Trend 1: Regularity 130nm 2.34μm2 90nm 1.0μm2 65nm 0.57μm2 45nm 0.346μm2 Sources: IBM, Intel; picture size not to scale Regular layout: reduces local variations and improves manufacturability Regular design: minimizes cost and enhances design predictability EEE525, ASU, Y. Cao Lecture 01 - 21 - Design Trend 2: Statistical 8 Circuit Speed (GHz) (variability shown as range) Nominal speed Normal speed Worst-case speed Path Timing 7 6 5 4 3 -3 T0 +3 …... Transistor Model Transistor 180 130 90 65 Technology Node (nm) Technology Node (nm) 45 L Vth Uncertainties are statistical in nature Deterministic design methodology wastes an excessive amount of resource EEE525, ASU, Y. Cao Lecture 01 - 22 - 11 Design Trend 3: Resilient PC (read-only) error bubble Stabilizer FF Razor FF Razor FF Razor FF Razor FF IF ID error bubble EX error bubble MEM WB (reg/mem) error bubble recover recover flushID recover flushID recover flushID Flush Control flushID Razor design, U Mich. Designs that detect and self-correct errors Careful use of redundancy and error correction use of redundancy and error correction Provides reliable computation layered on unreliable fabrics EEE525, ASU, Y. Cao Lecture 01 - 23 - More Radical Solutions… Aggressive voltage scaling joint with novel technologies – Example: Ultra low Vdd and Vth design with FinFET Neuromorphic design: let the machine “think” design: let the machine think Transition to post-silicon fabrication and devices DNA self-assembly, ASU EEE525, ASU, Y. Cao Carbon nano-tube RO, IBM Lecture 01 - 24 - 12 Summary EEE 525: design fundamentals and practices underlying the VLSI system integration Metrics: area, speed, power, reliability, and cost area speed power reliability and cost Challenges ahead: power, cost, and reliability Clear understanding from a circuit perspective Contact: yu.cao@asu.edu Office hours: TTh 10:30-12:00pm, GWC 336 Web access: http://my.asu.edu access: http://my EEE525, ASU, Y. Cao Lecture 01 - 25 - 13 ...
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