Lecture-02 - EEE 525 VLSI Design L-02 CMOS Technology...

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1 EEE 525: VLSI Design, L-02 CMOS Technology Scaling Spring 2010, ASU Yu (Kevin) Cao, [email protected] , GWC 336 Highlight CMOS evolution and scaling challenges Alternative materials St i d ili t h l Strained silicon technology Metal gate and high-K dielectrics Future opportunities Reading: Chapter 2 and 3 EEE525, ASU, Y. Cao Lecture 02 - 2 -
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2 Highlight CMOS evolution and scaling challenges Alternative materials St i d ili t h l Strained silicon technology Metal gate and high-K dielectrics Future opportunities Reading: Chapter 2 and 3 EEE525, ASU, Y. Cao Lecture 02 - 3 - First FET 1935 British Patent Issued to O. Heil EEE525, ASU, Y. Cao Lecture 02 - 4 -
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3 Semiconductor Evolution The first transistor The first integrated circuit 4004 Pentium® 4 EEE525, ASU, Y. Cao Lecture 02 - 5 - 3D Perspective of a MOSFET Polysilicon/Metal Aluminum/Copper MOSFET: Metal-Oxide-Semiconductor Field Effect Transistor Gate EEE525, ASU, Y. Cao Lecture 02 - 6 -
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4 Contemporary Bulk CMOS EEE525, ASU, Y. Cao Lecture 02 - 7 - Desirable Features of FET Low voltage (<1v) Large I on (>0.6mA/ m) Small I off (<3nA/ m) Small capacitance Reliability (lifetime > 10 yr) Compatibility with existing circuit architecture or a better new architecture (3 terminal, complimentary, i.e. drop-in replacement for CMOS) Compatibility with existing manufacturing technology infrastructure Easier to improve CMOS than replace it, but, there is always room for high-risk research... EEE525, ASU, Y. Cao Lecture 02 - 8 -
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5 Latest Scaling Trend (I) Source: Intel and ITRS EEE525, ASU, Y. Cao Lecture 08 - 9 - Latest Scaling Trend (II) Equivalent Oxide Thickness V DD and V th 3.5 4.0 4.5 250nm 1.6 2.0 250nm 180nm 130nm 10 30 50 70 90 110 130 0.0 0.5 1.0 1.5 2.0 2.5 3.0 32nm 180nm 130nm 45nm 65nm 90nm PTM Intel IBM TI Fujitsu TSMC EOT (nm) L (nm) 10 30 50 70 90 110 130 0.0 0.4 0.8 1.2 32nm 45nm 65nm 90nm PTM
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