Lecture-06 - EEE 525: VLSI Design, L-06 MOSFET Capacitance...

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1 EEE 525: VLSI Design, L-06 MOSFET Capacitance and Layout Spring 2010, ASU Yu (Kevin) Cao, [email protected] , GWC 336 Highlight MOSFET capacitances Gate capacitance S/D parasitic capacitance Layout and analysis basics Design rules Correct, compact, and reliable Reading: Chapter 2 EEE525, ASU, Y. Cao Lecture 06 - 2 -
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2 Highlight MOSFET capacitances Gate capacitance S/D parasitic capacitance Layout and analysis basics – Design rules – Correct, compact, and reliable Reading: Chapter 2 EEE525, ASU, Y. Cao Lecture 06 - 3 - Dynamic Behavior of MOSFET V V Vout R p V DD in out C L Current driving a load capacitor Signal delay: CV/I out (a) Low-to-high C L V DD EEE525, ASU, Y. Cao Lecture 06 - 4 - MOSFET: a voltage-controlled current source, with parasitic capacitance V out R n (b) High-to-low C L
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3 MOSFET Capacitances V GS + - V DS + G C GS C GD n+ n+ p- substrate n+ n+ - C GB B SD C DB C SB i ij V Q C G GS V Q C EEE525, ASU, Y. Cao Lecture 06 - 5 - Four electrical nodes of a MOSFET transistor Parasitic capacitances: between two nodes, except S and D (totally 10) j S V GS + - Gate Capacitance: Off Region C ox Gate and S/D regions overlap each other to guarantee the channel n+ n+ p- substrate n+ n+ n+ n+   dep ox D GB C C L L W C 2 guarantee the channel connection eff L EEE525, ASU, Y. Cao Lecture 06 - 6 - W L D ox ox ox t C f ox D GD GS C C WL C C
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4 Gate Capacitance: Linear Region V GS V DS S G GS V Q C n+ n+ n+ o eff GD GS C WL C C  D th GS ox inv G V V V C Q Q EEE525, ASU, Y. Cao Lecture 06 - 7 - ov ox C 2 The capacitance splits equally in the linear region What about C GB ?
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This note was uploaded on 03/11/2010 for the course EE 525 taught by Professor Yucao during the Spring '10 term at Punjab Engineering College.

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Lecture-06 - EEE 525: VLSI Design, L-06 MOSFET Capacitance...

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