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EEE 525: VLSI Design, L-08
Inverter Design
Spring 2010, ASU
Yu (Kevin) Cao,
[email protected]
, GWC 336
Highlight
Inverter basics
Static behaviors
–
Voltage Transfer Curve (VTC)
–
Static noise margin
Dynamic behaviors
–
Signal speed
–
Power consumption
EEE525, ASU, Y. Cao
Lecture 08
- 2 -
Reading: Chapter 1 and 4

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Highlight
Inverter basics
Static behaviors
–
Voltage Transfer Curve (VTC)
–
Static noise margin
Dynamic behaviors
– Signal speed
– Power consumption
EEE525, ASU, Y. Cao
Lecture 08
- 3 -
Reading: Chapter 1 and 4
A CMOS Inverter
V
DD
V
DD
OUT
in
GND
V
in
V
out
C
L
V
in
V
out
C
L
EEE525, ASU, Y. Cao
The simplest logic unit of digital circuits
Layout
Circuit schematic
Logic gate
Lecture 08
- 4 -

3
Logic Operations
V
in
V
out
In
Out
01
1
0
C
L
V
out
R
p
DD
EEE525, ASU, Y. Cao
(a) Low-to-high
C
L
(b) High-to-low
n
Lecture 08
- 5 -
Voltage Transfer Curve
(V)
All W
P
=1.4
μ
m
W
N
=10
m
W
N
=5
m
W
N
=1
m
V
M
EEE525, ASU, Y. Cao
Logical switching threshold voltage:
V
M
, where V
in
=V
out
V
in
(V)
Lecture 08
- 6 -

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Operation of a CMOS Inverter
I
P
V
DD
V
out
2.5
NMOS off
PMOS linear
NMOS saturation
1
V
in
V
out
I
N
I
N
=
I
P
1.25
PMOS linear
NMOS saturation
PMOS saturation
NMOS linear
PMOS saturation
NMOS linear
2
3
4
EEE525, ASU, Y. Cao
NMOS: V
gs
=V
in
, V
ds
=V
out
PMOS: V
gs
=V
in
-V
DD
, V
ds
=V
out
-V
DD
V
in
0
0
1.25
2.5
PMOS off
5
Lecture 08
- 7 -
V
M
Calculation
thP
dsatP
DD
M
P
ox
satP
thN
dsatN
M
N
ox
satN
V
V
V
V
W
C
v
V
V
V
W
C
v
V
V
V
V
V
r
r
r
r
V
DD
dsatP
dsatN
thP
thN
M
1
N
satN
P
satP
W
v
W
v
r
where
If the process of NMOS process is symmetrical to that of PMOS
EEE525, ASU, Y. Cao
Note 1
: for PMOS, V
gs
, V
dsat
, and V
th
are negative values
(i.e., V
thN
= -V
thP
, V
dsatN
= -V
dsatP
) and
r
=1,
then,
2
DD
M
V
V
Lecture 08
- 8 -