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Lecture-09

# Lecture-09 - EEE 525 VLSI Design L-09 Combinational Static...

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1 EEE 525: VLSI Design, L-09 Combinational Static Logic Design Spring 2010, ASU Yu (Kevin) Cao, [email protected] , GWC 336 Highlight Combinational logic Logic gate and path construction CMOS implementation Delay analysis Alternative implementation: FPGA Reading: Chapter 6 EEE525, ASU, Y. Cao Lecture 09 - 2 -

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2 Highlight Combinational logic Logic gate and path construction CMOS implementation Delay analysis Alternative implementation: FPGA Reading: Chapter 6 EEE525, ASU, Y. Cao Lecture 09 - 3 - Combinational vs. Sequential Logic Combinational Logic Out In Combinational Logic Out In Combinational Sequential Output = f (In) Circuit Circuit State Output = f (In, Previous state) EEE525, ASU, Y. Cao Lecture 09 - 4 - Combinational: output is a function of present inputs (no memory) Sequential: output is also dependent on previous states (need memory to store data)
3 Elementary Boolean Gates Logic and math are equivalent All math functions can be determined using these 3 George Boole, 1815-1864 (“ A Calculus of Logic ”) determined using these 3 primary Boolean logic operators: AND, OR, and NOT x y And(x,y) 0 0 0 0 1 0 1 0 0 1 1 1 x y Or(x,y) 0 0 0 0 1 1 1 0 1 1 1 1 x Not(x) 0 1 1 0 EEE525, ASU, Y. Cao Lecture 09 - 5 - Programmable Logic Array a b c and active fuse blown fuse legend: and or f(a,b,c) 8 and terms connected to the same 3 inputs . . . single or term connected to the outputs of 8 and terms The ON/OFF states determines which gates involve in the computation PLA implementation of f(a,b,c)= a b c + a b c _ _ _ EEE525, ASU, Y. Cao Lecture 09 - 6 -

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4 Example: Multiplexer (Mux) a b Mux a b sel out 0 0 0 0 0 0 1 0 b sel out f sel 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 sel out 0 a 1 b a Logic: uniquely defined by the truth table Implementation: a single gate, or a path with multiple gates Timing of a CMOS path: sum of each gate delay on the path EEE525, ASU, Y. Cao Lecture 09 - 7 - Highlight Combinational logic Logic gate and path construction CMOS implementation Delay analysis Alternative implementation: FPGA Reading: Chapter 6 EEE525, ASU, Y. Cao Lecture 09 - 8 -
5 Static Logic Style V DD a b PUN V DD f (a,b,…,c) c a b c PDN f (a,b,…,c) a b c PDN S i D i EEE525, ASU, Y. Cao Lecture 09 - 9 - Static: output is always connected to VDD or GND Dynamic: not always connected; data can leak away at standby Static Dynamic Advantages of CMOS Implementation Full rail-to-rail swing; high noise margins

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