Lecture-10 - 1 EEE 525: VLSI Design, L-10 EEE 525: VLSI...

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Unformatted text preview: 1 EEE 525: VLSI Design, L-10 EEE 525: VLSI Design, L-10 Arithmetic Circuits Design Arithmetic Circuits Design Spring 2010, ASU Yu (Kevin) Cao, yu.cao@asu.edu , GWC 336 Highlight Highlight Arithmetic circuits in a VLSI system One-bit full adder design – Logic definition – Circuit implementation Multiple-bit adder design – Structure optimizations Other ALU circuits: EEE525, ASU, Y. Cao Lecture 10- 2 - Other ALU circuits: – Multiplier – Shifter Reading: Chapter 10 2 Project Overview Project Overview Design team: 2 people, equal contribution Objective: a 32-bit ALU for a low-power processor Goal: minimize power consumption within a performance Goal: minimize power consumption within a performance constraint Design decisions: adder, multiplexer, shifter, register file, multiple-bit structure, sizing, V DD , process corners Phase I: schematic design of main ALU circuit units Phase II: layout and verification; register file design EEE525, ASU, Y. Cao Lecture 10- 3 - Phase II: layout and verification; register file design Grade: mainly based on the ranking of power A 32-Bit ALU A 32-Bit ALU At the heart of a microprocessor Three main components: 9-1 Mux 9-1 Mux FF FF a b – Arithmetic block: 32-bit general purpose adder – mux and shifter: extend the ALU functionality – Register file: 32-bit, 2 read and 1 write ports Shifter 2-1 Mux Adder A B EEE525, ASU, Y. Cao Lecture 10- 4 - The entire circuit is synchronized by the clock, through both FFs and RF Register File with 2 read and 1 write ports Adder Sum 3 Discussion: Design Strategy Discussion: Design Strategy Design constraints of ALU: – Delay: 10ns, with a 30fF C L at the output bit – Noise margin: 20% of V DD – Energy: averaged from five test cases Process technology: fixed (no tuning of V th , L, and T ox ) Gate: various styles and sizes – Prepare a set of commonly used gates, which will help your layout in Phase II Architecture: various choices do matte EEE525, ASU, Y. Cao Lecture 10- 5 - Architecture: various choices do matter – Again, a scalable architecture will help your layout Start from a high performance design, then reduce V DD , size, etc. to approach the constraints; try to balance all the data paths Highlight Highlight Arithmetic circuits in a VLSI system One-bit full adder design – Logic definition – Circuit implementation Multiple-bit adder design – Structure optimizations Other ALU circuits: EEE525, ASU, Y. Cao Lecture 10- 6 - Other ALU circuits: – Multiplier – Shifter Reading: Chapter 10 4 A Digital Processor A Digital Processor MEMORY UT DATAPATH CONTROL INPUT-OUTPU EEE525, ASU, Y. Cao Control: finite-state-machine, counters, etc....
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Lecture-10 - 1 EEE 525: VLSI Design, L-10 EEE 525: VLSI...

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