Lecture-13 - 1 EEE 525: VLSI Design, L-13 EEE 525: VLSI...

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Unformatted text preview: 1 EEE 525: VLSI Design, L-13 EEE 525: VLSI Design, L-13 Low Power Design: Active Power Low Power Design: Active Power Spring 2010, ASU Yu (Kevin) Cao, yu.cao@asu.edu , GWC 336 Highlight Highlight Motivation and general principles Active power reduction – Logic design – Circuit optimization: sizing and multiple-V DD – Concurrency: pipeline and multiple-core – Dynamic voltage scaling Reading: Chapter 6 and 10 Additional reading: – A. Chandrakasan and R. Brodersen, “Minimizing power consumption in digital CMOS circuits” EEE525, ASU, Y. Cao Lecture 13- 2 - 2 Highlight Highlight Motivation and general principles Active power reduction – Logic design – Circuit optimization: sizing and multiple-V DD – Concurrency: pipeline and multiple-core – Dynamic voltage scaling Reading: Chapter 6 and 10 Additional reading: – A. Chandrakasan and R. Brodersen, “Minimizing power consumption in digital CMOS circuits” EEE525, ASU, Y. Cao Lecture 13- 3 - The Power Challenge (1) The Power Challenge (1) Crucial for high-performance applications – Limits the performance and cooling cost EEE525, ASU, Y. Cao Lecture 13- 4 - 3 The Power Challenge (2) The Power Challenge (2) Crucial for portable electronics – Determines battery lifetime, mobility, and computation EEE525, ASU, Y. Cao Lecture 13- 5 - Energy within 1cm 3 Energy within 1cm 3 P avg =20W (2% of the weight, 20% of P) Density: ~ 15mW/cm 3 J. Rabaey, UCB EEE525, ASU, Y. Cao Lecture 13- 6 - 4 Power Sources Power Sources Active power – Charging capacitors – Short-circuit power – Impact ionization Leakage power – S/D leakage (Ids, junction, etc.) – Gate leakage – Biasing currents EEE525, ASU, Y. Cao Lecture 13- 7 - Low Power Design Space Low Power Design Space Constant Throughput/Latency Variable Throughput/Latency Power Design Time Sleep Mode Run Time Active Logic design Gate sizing Low V DD Multi-V DD Pipeline Clock gating DVS, DFS Leakage Stack effects Multi-V th Power gating Multi-V DD , V th V DD ramping Variable V th EEE525, ASU, Y. Cao Lecture 13- 8 - 5 Highlight Highlight Motivation and general principles Active power reduction – Logic design – Circuit optimization: sizing and multiple-V DD – Concurrency: pipeline and multiple-core – Dynamic voltage scaling Reading: Chapter 6 and 10 Additional reading: – A. Chandrakasan and R. Brodersen, “Minimizing power – A....
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This note was uploaded on 03/11/2010 for the course EE 525 taught by Professor Yucao during the Spring '10 term at Punjab Engineering College.

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Lecture-13 - 1 EEE 525: VLSI Design, L-13 EEE 525: VLSI...

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