This preview shows pages 1–2. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: and C, such that S is 0 if one of two inputs is 1, and C is 0 if two inputs are 1. (20%) 4. Consider the following structure of logic circuits. 2 Assume that the minimum sizing of NMOS is 2 unit (n = 2) and PMOS is 3 units (p = 3) with channel length 0.15 m (L = 0.15 m). Determine the width of each transistor, Q A , Q B , Q C , Qe , and Qp . (20%) 5. Consider the following logic diagram of ANDORINVERT gates, IC model SN74LS51, from Texas Instrument. Answer the following questions: a. Write the logic (Boolean) equation of the circuit above. (5%) b. Use complementary CMOS design to draw the circuit. Show pulldown network, pullup network, VDD, and GND. (15%)...
View
Full
Document
This note was uploaded on 03/11/2010 for the course EEE 4343 taught by Professor Dr.fan during the Spring '10 term at FIU.
 Spring '10
 Dr.Fan

Click to edit the document details