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Unformatted text preview: and C, such that S is 0 if one of two inputs is 1, and C is 0 if two inputs are 1. (20%) 4. Consider the following structure of logic circuits. 2 Assume that the minimum sizing of NMOS is 2 unit (n = 2) and PMOS is 3 units (p = 3) with channel length 0.15 μm (L = 0.15 μm). Determine the width of each transistor, Q A , Q B , Q C , Qe , and Qp . (20%) 5. Consider the following logic diagram of ANDORINVERT gates, IC model SN74LS51, from Texas Instrument. Answer the following questions: a. Write the logic (Boolean) equation of the circuit above. (5%) b. Use complementary CMOS design to draw the circuit. Show pulldown network, pullup network, VDD, and GND. (15%)...
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 Spring '10
 Dr.Fan
 Logic gate, power supply, particular inverter design

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