eee4343_midterm-II_spring10 - and C, such that S is 0 if...

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1 EEE-4343 Midterm-II February 23, 2010 (11:00 am – 12:15 pm) Open-book, open-notes, in-class exam (calculators ok, but no computers) Name: ______________________________________________________ SID: ______________________________________________________ 1. For a particular inverter design using a power supply V DD , V OL = 0.2V DD , V OH = 0.5V DD , V IL = 0.4V DD , and V IH = 0.4V DD . For a minimum noise margin of 0.5V, what value of V DD is required? (20%) 2. In a particular logic family, operating with a 3V power supply, the basic inverter draws a current of 29 μA in one state and 1 μA in the other. When the inverter is switching at the rate of 200 MHz, the average supply current becomes 100 μA. Estimate the equivalent capacitance at the output node of the inverter. (20%) 3. Design a CMOS full-adder circuit with two inputs A and B, and two outputs S
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Unformatted text preview: and C, such that S is 0 if one of two inputs is 1, and C is 0 if two inputs are 1. (20%) 4. Consider the following structure of logic circuits. 2 Assume that the minimum sizing of NMOS is 2 unit (n = 2) and PMOS is 3 units (p = 3) with channel length 0.15 m (L = 0.15 m). Determine the width of each transistor, Q A , Q B , Q C , Qe , and Qp . (20%) 5. Consider the following logic diagram of AND-OR-INVERT gates, IC model SN74LS51, from Texas Instrument. Answer the following questions: a. Write the logic (Boolean) equation of the circuit above. (5%) b. Use complementary CMOS design to draw the circuit. Show pull-down network, pull-up network, VDD, and GND. (15%)...
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This note was uploaded on 03/11/2010 for the course EEE 4343 taught by Professor during the Spring '10 term at FIU.

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eee4343_midterm-II_spring10 - and C, such that S is 0 if...

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