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Unformatted text preview: Low Power Design Essentials 2008 11 Jan M. Rabaey Low Power Design Essentials 2008 Chapter 11 UltraLow Power/Voltage Design Low Power Design Essentials 2008 11 Chapter Outline Rationale Lower Bounds on Computational Energy Subthreshold Logic Moderate Inversion as a Tradeoff Revisiting Logic Gate Topologies Summary Low Power Design Essentials 2008 11 Rationale Continued increase of computational density must be combined with decrease in energy/operation (EOP). Further scaling of supply voltage essential to accomplish that The only other option is to keep on reducing activity Some key questions: How far can the supply voltage be scaled? What is the minimum energy per operation that can be obtained theoretically and practically? What to do about the threshold voltage and leakage? How to practically design circuits that approach the minimum energy bounds? Low Power Design Essentials 2008 11 Opportunities for UltraLow Voltage Number of applications emerging that do not need high performance, only extremely low power dissipation Examples: Standby operation for mobile components Implanted electronics and artificial senses Smart objects, fabrics and etextiles Need power levels below 1 mW (even W in certain cases) Low Power Design Essentials 2008 11 Minimum Operational Voltage of Inverter Swanson, Meindl (April 1972) Further extended in Meindl (Oct 2000) Limitation: gain at midpoint > 1 Cox : gate capacitance Cd : diffusion capacitance n : slope factor For ideal MOSFET (60 mV/decade slope): ) 1 ln( ) ( 2 (min) ) 2 ln( ) ( 2 (min) n q kT V C C q kT V DD ox d DD + = + = V q kT q kT V DD 036 . 38 . 1 ) 2 ln( 2 (min) = = = at 300 K or [Ref: R. Swanson, JSSC72; J. Meindl, JSSC00] IEEE 1972 Low Power Design Essentials 2008 11 Subthreshold Modeling of CMOS Inverter From Chapter 2: = =q kT V q kT n V q kT V q kT n V V S DS DS GS DS TH GS e e I e e I I 1 1 (DIBL can be ignored at low voltages) with q kT n V S TH e I I= Low Power Design Essentials 2008 11 Subthreshold DC model of CMOS Inverter Assume NMOS and PMOS are fully symmetrical and all voltages normalized to the thermal voltage T = kT / q ( xi = Vi / T; xo = Vo/ T; xD = VDD / T) The VTC of the inverter for NMOS and PMOS in subthreshold can be derived: [Ref: E. Vittoz, CRC05] ) 2 4 ) 1 ( 1 ln( 2 D x D o Ge G G x x+++ = with n x x D i e G / ) 2 (= so that ) 2 ( ) 1 ( 2 o D o D D o D o x x x x x x x x V e e e n e e e A= n e A D x V / ) 1 ( 2 / max= and For  AVmax  = 1: xD = 2ln( n +1) Low Power Design Essentials 2008 11 Results from Analytical Model 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 1 2 3 4 5 6 7 n x d Amax =1 Amax =2 Amax =4 Amax =10 Normalized VTC for n =1.5 as a function of VDD ( xd ) Subthreshold Inverter Minimum supply voltage for a given maximum gain as a function of the slope factor n...
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 Spring '10
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