Kahng-ECE260BRoadmap-100121

Kahng-ECE260BRoadmap-100121 - Andrew B. Kahng Professor of...

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Unformatted text preview: Andrew B. Kahng Professor of CSE and ECE, UC San Diego [email protected] http://vlsicad.ucsd.edu/ The Technology Roadmap ECE 260B / CSE 241A Guest Lecture 2 Andrew B. Kahng, UCSD ECE 260B, January 21, 2010 emiconductor Technology Trends Performance Power Integration Cost Figures courtesy Intel 3 Andrew B. Kahng, UCSD ECE 260B, January 21, 2010 hat Drives Semiconductor Technology? Modern cellphone chip: 2+ processors, modem, graphics and video engines, DSPs in 8mm x 8mm 4 Andrew B. Kahng, UCSD ECE 260B, January 21, 2010 hat Does the IC Do? GOPS Required performance for multimedia processing (GOPS: Giga Operations Per Sec) 2007 ITRS SOC Consumer-Stationary Driver: 220 TFlops on a single chip by 2022 0.01 0.1 1 10 Video ideo udio udio Voice oice ommunication ommunication ecognition ecognition raphics raphics FAX Modem 2D Graphics 3D Graphics MPEG Dolby-AC3 JPEG MPEG1 Extraction MPEG2 Extraction MP/ML MP/HL Compression VoIP Modem Word Recognition Sentence Translation 100 Voice Auto Translation 10Mpps 100Mpps MPEG4 Face Recognition Voice Print Recognition SW Defined Radio Moving Picture Recognition 5 Andrew B. Kahng, UCSD ECE 260B, January 21, 2010 ow Is It Connected? Wire Via Global (up to 5) Intermediate (up to 4) Local (2) Passivation Dielectric Etch Stop Layer Dielectric Capping Layer Copper Conductor with Barrier/Nucleation Layer Pre Metal Dielectric Tungsten Contact Plug EMATECH Prototype BEOL (“back end of the line”) metal stack, 2000 6 Andrew B. Kahng, UCSD ECE 260B, January 21, 2010 ow Is It Manufactured? Sub-wavelength optical lithography Slide courtesy of Numerical Technologies, Inc. 7 Andrew B. Kahng, UCSD ECE 260B, January 21, 2010 (Mask Shapes Used in Lithography) 8 Andrew B. Kahng, UCSD ECE 260B, January 21, 2010 any Interesting Technology Trends Lithography Minimum feature size scales by 0.7x every three (two?) years Add another pair of layers: last generation’s chip = this generation’s module Interconnect delay doesn’t scale well Dominates system performance Coupling gets worse timing uncertainty and design guardband Multiple clock cycles needed to cross chip whether 3 or 15 not as important as “multiple” being > 1 How does manufacturing process enter into picture? Lower-permittivity dielectrics organics to aerogels to air gaps Copper interconnects resistivity, reliability Planarization more layers are stackable 9 Andrew B. Kahng, UCSD ECE 260B, January 21, 2010 any Interesting Design Challenges Result Manufacturability (chip can't be built) antenna rules minimum area rules for stacked vias CMP (chemical mechanical polishing) area fill rules layout corrections for optical proximity effects in subwavelength lithography Signal integrity (chip fails timing constraints) crosstalk induced errors timing dependence on crosstalk IR drop on power supplies Reliability (chip fails in the field) electromigration on power supplies hot carrier effects on devices...
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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Kahng-ECE260BRoadmap-100121 - Andrew B. Kahng Professor of...

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