Bohr - 2009 ISSCC The New Era of Scaling in an SoC World...

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1 The New Era of Scaling in an SoC World Mark Bohr Intel Senior Fellow Logic Technology Development 2009 ISSCC
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2 The End of Scaling is Near? “Optical lithography will reach its limits in the range of 0.75-0.50 microns” “Minimum geometries will saturate in the range of 0.3 to 0.5 microns” “X-ray lithography will be needed below 1 micron” “Minimum gate oxide thickness is limited to ~2 nm” “Copper interconnects will never work” “Scaling will end in ~10 years” Perceived barriers are meant to be surmounted, circumvented or tunneled through
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3 Outline • Transistor Scaling • Microprocessor Evolution • Vision of the Future
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4 0.01 0.1 1 10 1970 1980 1990 2000 2010 2020 Microns CPU Transistor Count 2x every 2 years 10 3 10 5 10 9 10 7 Scaling Trends Transistor dimensions scale to improve performance, reduce power and reduce cost per transistor
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5 0.01 0.1 1 10 1970 1980 1990 2000 2010 2020 Microns 45nm 65nm 32nm Feature Size 0.7x every 2 years CPU Transistor Count 2x every 2 years 10 3 10 5 10 9 10 7 Scaling Trends Transistor dimensions scale to improve performance, reduce power and reduce cost per transistor
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6 MOSFET Scaling R. Dennard, IEEE JSSC, 1974 Device or Circuit Parameter Scaling Factor Device dimension tox, L, W 1/ κ Doping concentration Na κ Voltage V 1/ κ Current I 1/ κ Capacitance ε A/t 1/ κ Delay time/circuit VC/I 1/ κ Power dissipation/circuit VI 1/ κ 2 Power density VI/A 1 Classical MOSFET scaling was first described in 1974
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7 30 Years of MOSFET Scaling Gate Length: 1.0 μ m 35 nm Gate Oxide Thickness: 35 nm 1.2 nm Operating Voltage: 4.0 V 1.2 V 1 μ m Dennard 1974 Intel 2005 Classical scaling ended in the early 2000s due to gate oxide leakage limits
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8 90 nm Strained Silicon Transistors High Stress Film NMOS SiGe SiGe PMOS SiN cap layer SiGe source-drain Tensile channel strain Compressive channel strain Strained silicon provided increased drive currents, making up for lack of gate oxide scaling
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9 High-k + Metal Gate Transistors 65 nm Transistor 45 nm HK+MG High-k + metal gate transistors break through gate oxide scaling barrier SiO 2 dielectric Hafnium-based dielectric Polysilicon gate electrode Metal gate electrode
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10 1 10 100 1000 0.4 0.6 0.8 1.0 1.2 1.4 1.6 I ON (mA/um) I OFF (nA/um) 1.0 V 65nm 45nm 1 10 100 1000 0.6 0.8 1.0 1.2 1.4 1.6 1.8 I ON (mA/um) 1.0 V 65nm 45nm +12% +50% NMOS PMOS 100x 5x Transistor Performance Increase 45 nm HK+MG provides average 30% drive current increase or >5x I OFF leakage reduction Ref. K. Mistry, IEDM ’07
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11 Gate Leakage Reduction HK+MG significantly reduces gate leakage 0.00001 0.0001 0.001 0.01 0.1 1 10 100 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 VGS (V) Norm alized G ate Leakage SiON/Poly 65nm HiK+MG 45nm NMOS PMOS HiK+MG 45nm SiON/Poly 65nm 25x 1000x
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12 0 2 4 6 8 10 12 65nm 45nm Normalized Cell Leakage I GATE I OFF I JUNCT 1.0V 25C 10x Bitcell Leakage Reduction SRAM bitcell leakage reduced ~10x
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13 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 180nm 130nm 90nm 65nm 45nm
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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Bohr - 2009 ISSCC The New Era of Scaling in an SoC World...

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