bohrISSCC09

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ISSCC 2009 / February 9, 2009 / 10:35 AM 23 DIGEST OF TECHNICAL PAPERS 1 1.3 The New Era of Scaling in an SoC World Mark Bohr, Senior Fellow, Intel, Hillsboro, OR 1. Introduction MOSFET scaling has served our industry well for more than three decades by providing significant improvements in transistor performance, power and cost-per-transistor. Along this path many barriers to continued scaling have been perceived as insurmountable and the end of scaling was often predicted. But, perceived barriers are meant to be surmounted, circumvent- ed or tunneled through, and the combined ingenuity of our industry has pushed transistor technology and microprocessor design well beyond what anyone thought possible a few decades ago. The scaling path that we have been on has not been a straight evolutionary path, it has taken some unex- pected turns in direction. Our challenge in this new era of scaling is to rec- ognize the coming revolutionary changes and opportunities and to prepare to utilize them. 2. Transistor Scaling Classical MOSFET scaling was first described by Dennard in 1974 [1]. The combination of Moore’s Law and Dennard’s scaling methodology has pro- vided our industry with many generations of smaller faster transistors, and higher performance microprocessors (Figure 1.3.1). Classical MOSFET scaling techniques were followed successfully until around the 90nm gen- eration, when gate-oxide scaling started to slow down due to increased gate leakage. The limitation posed by gate leakage became so severe that there was essentially no gate-oxide thickness scaling from the 90nm to the 65nm generation, and many companies converged on a SiO 2 thickness close to 1.2nm for their high-performance logic process. When gate-oxide thickness can no longer be scaled, then other key MOSFET parameters, such as sup- ply voltage, can not be scaled and still expect to deliver improved transistor performance. Without new inventions, MOSFET scaling and Moore’s Law were threatened with the likelihood of coming to an end. One of the first significant transistor innovations in the past decade was the introduction in 2003 of strained-silicon technology to enhance transistor performance for Intel’s 90nm microprocessors [2, 3]. The 65nm generation introduced in 2005 further improved these strain techniques to increase transistor performance, even though gate-oxide thickness stayed at rough- ly the same 1.2nm value to avoid increased leakage current [4]. Strained sil- icon is an example of a revolutionary technology that provided improved performance without following classical MOSFET scaling methods. Although strained silicon provided valuable performance enhancements for 90nm and 65nm generations, we could not ignore the need to scale gate- oxide thickness, and the need to reduce gate-oxide leakage, on future tech- nologies. Intel’s 45nm logic technology was the first to introduce high- κ dielectric with metal-gate transistors for improved performance and reduced leakage [5, 6]. A hafnium-based dielectric replaced SiO 2 to provide
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