Ch4_DT-Circuits

Ch4_DT-Circuits - Optimizing Power @ Design Time Circuits...

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Unformatted text preview: Optimizing Power @ Design Time Circuits Jan M. Rabaey Dejan Marković Borivoje Nikolić Low Power Design Essentials ©2008 Low Power Design Essentials Chapter 4 4.1 Chapter Outline Optimization framework for energy-delay trade-off Dynamic power optimization – – – § § Multiple supply voltages Transistor sizing Technology mapping Multiple thresholds Transistor stacking § Static power optimization – – Low Power Design Essentials 4.2 Energy/Power Optimization Strategy § § § For given function and activity, an optimal operation point can be derived in the energy-performance space Time of optimization depends upon activity profile Different optimizations apply to active and static power Fixed Activity Active Design time Static Variable Activity No Activity - Standby Run time Sleep Low Power Design Essentials 4.3 Energy-Delay Optimization and Trade-off Energy/op Unoptimized design Trade-off space Em ax Emi n Maximize throughput for given energy or Minimize energy for given throughput Other important metrics: Area, Reliability, Reusability Low Power Design Essentials 4.4 Dmi n Obj100 Dm ax Delay The Design Abstraction Stack A very rich set of design parameters to consider! It helps to consider options in relation to their abstraction layer System/Application Software (Micro-)Architecture This Chapter Choice of algorithm Amount of concurrency Parallel versus pipelined, general purpose versus application specific logic family, standard cell versus custom sizing, supply, thresholds Bulk versus SOI 4.5 Logic/RT Circuit Device Low Power Design Essentials Optimization Can/Must Span Multiple Levels Architecture Micro-Architecture Circuit (Logic & FFs) Design optimization combines top-down and bottom-up: “meet-in-the-middle” Low Power Design Essentials 4.6 Energy-Delay Optimization Energy/op topology A topology B Obj102 Delay Energy/op topology A topology B Obj101 Delay Globally optimal energy-delay curve for a given function Low Power Design Essentials 4.7 Some Optimization Observations Energy ∂E / ∂A SA ∂D / ∂A A= = S A S B (A0,B0 ) f (A,B0) f (A0,B) A0 Delay D 0 Energy-Delay Sensitivities Low Power Design Essentials [Ref: V. Stojanovic, 4.8 Finding the Optimal Energy-Delay Curve Pareto-optimal: the best that can be achieved without disadvantaging at least one metric. f (A1,B) ∆D ∆E = SA∙(ª ∆D) (A0,B 0) f (A,B0) Energy + SB∙∆D On the optimal curve, all sensitivities must be equal Low Power Design Essentials 4.9 D 0 Delay f (A0,B) Reducing Active Energy @ Design Time Eactive ~ α ⋅ C L ⋅ Vswing ⋅ VDD Pactive ~ α ⋅ C L ⋅ Vswing ⋅ VDD ⋅ f § Reducing voltages – – Lowering the supply voltage (VDD) at the expense of clock speed Lowering the logic swing (Vswing) Slows down logic Reducing switching activity through transformations Reducing glitching by balancing logic § Reducing transistor sizes (CL) – § Reducing activity (α) – – Low Power Design Essentials 4. Observation § § Downsizing and/or lowering the supply on the critical path lowers the operating frequency Downsizing non-critical paths reduces energy for free, but – – Narrows down the path delay distribution Increases impact of variations, impacts robustness # of paths tp (path) # of paths target delay target delay tp (path) Low Power Design Essentials 4. Circuit Optimization Framework minimize Energy (VDD, VTH, W) subject to Delay (VDD, VTH, W) ≤ Dcon Constraints VDDmin < VDD < VDDmax VTHmin < VTH < VTHmax Wmin < W Reference case – topology A Energy/op § topology B Obj105 Dmin sizing @ VDDmax, VTHref Delay Low Power Design Essentials [Ref: V. Stojanovic, 4. Optimization Framework: Generic Network VD D,i VDD,i +1 i+1 i C i γC i C w Ci+ 1 Gate in stage i loaded by fanout (stage i+1) Low Power Design Essentials 4. Alpha-power based Delay Model K dVDD γC i +Cw + Ci +1 1 Ci′+1 t p= ( ) = τ nom (1 + ⋅ ) αd γCi γ Ci (VDD − Von ) Fit parameters: Von, å d, Kd, γ 4 simulati simulati 3 on on mod 5 mod . 0 el el 53 τ nom = Vo = 0.37 4 2 6 ps 0 V α= n . d γ= 1.53 3 52 1.35 0 1 2 . 0 t p 51 1 0 0 (90nm . 0 5 0 0 technology) 0 0 0 0 1 0 2 4 6 r . . . . V D .e Fanout D 5 6 7/8 9 f D D (Ci+1/ VDDref = 1.2V, technology 90 nm Ci) V 6 0 FO4 delay (norm.) Delay (ps) 8 1 0 Low Power Design Essentials 4. Combined with Logical Effort Formulation For Complex Gates fi gi t p = τ nom ( pi + ) γ § § § § Parasitic delay pi – depends upon gate topology Electrical effort fi ≈ Si+1/Si Logical effort gi – depends upon gate topology Effective fanout hi = figi Low Power Design Essentials [Ref: I. Sutherland, Morgan-Kaufman’99] 4. Dynamic Energy Edyn = (γCi + Cw + Ci +1 ) ⋅VDD ,i = Ci (γ + f i′) ⋅ VDD ,i 2 2 Ci = K e S i VD D,i f i′ = (Cw + Ci +1 ) / Ci = Si′+1 / S i VDD,i +1 i+1 i C i γ Χι C w 2 Ci +1 2 Ei = K e Si (VDD ,i −1 + γVDD ,i ) = energy consumed by logic gate i Low Power Design Essentials 4. Optimizating Return on Investment (ROI) Depends on Sensitivity (M E/ª D) § Gate Sizing ∂E ∂D § ∂Si ∂Si Ei =− τ nom (hi − hi −1 ) for equal h (Dmin) Supply Voltage ∂E ∂D ∂VDD ∂VDD Von 2 ⋅ (1 − ) E VDD =− ⋅ D α − 1 + Von d VDD max at VDD(max) (Dmin) Low Power Design Essentials 4. Example: Inverter Chain § Properties of inverter chain – – Single path topology Energy increases geometrically from input to output 1 S1 = 1 § S 2 S 3 … S N CL Goal – Find optimal sizing S = [S1, S2, …, SN], supply voltage, and buffering strategy to achieve the best energy-delay tradeoff Low Power Design Essentials 4. Inverter Chain: Gate Sizing 2 5 2 0 1 5 1 0 5 0 1 2 3 45 stage 6 nom op t d effective fanout, h in c = 50% 30 % 10 % 1 % 0 % Si −1 ⋅ Si +1 Si = 1 + µSi −1 2 2 ⋅ K e ⋅ VDD µ=− τ nom ⋅ FS Ei FS ∝ hi − hi −1 2 [Ref: Ma, JSSC’94] 7 § § Variable taper achieves minimum energy Reduce number of stages at large dinc 4. Low Power Design Essentials Inverter Chain: VDD Optimization 0% 1.0 nom D D 0.8 0.6 0.4 0.2 0 1 2 nom opt 3 d in c 1% 10% 30% = 50% V D D /V 4 5 stage 6 7 § § VDD reduces energy of the final load first Variable taper achieved by voltage scaling 4. Low Power Design Essentials Inverter Chain: Optimization Results 1 . 0 . 0 8 . 6 0 . 0 4 . 20 0 1 0 08 0 6 0 4 0 2 0 0 1 0 § n( c Parameter c % the largest sensitivity has the with ) potential for energy reduction 2 0 di 3 0 4 0 5 0 energy reduction (%) S g V 2 D V c D V D D Sensitivity (norm) 01 0 in 2 0 d 3 0 4 0 5 0 ( largest % ) § Two discrete supplies mimic per-stage VDD 4. Low Power Design Essentials Example: Kogge-Stone Tree Adder (A15, B15) S15 § Tree adder – – – Long wires Re-convergent paths Multiple active outputs (A0, B0) Cin S0 Low Power Design Essentials [Ref: P. Kogge, Trans. 4. Tree Adder: Sizing vs. Dual-VDD Optimization § Reference design: all paths are critical reference D=Dmin sizing: E (-54%) dinc=10% 2Vdd: E (27%) dinc=10% § Internal energy x – S more effective than VDD 4. S: E(-54%), 2Vdd: E(-27%) at dinc = 10% Low Power Design Essentials Tree Adder: Multi-dimensional Search 1 0. 8 Energy / Eref 0. 6 0. 4 0. 2 0 0. 4 0. 6 0. 8 1 1. 2 1. 4 Referenc e VDD, VTH S, VDD S, VTH S, VDD, VTH § § Delay / Dmin Can get pretty close to optimum with only 2 variables Getting the minimum speed or delay is very expensive 4. 1. 6 1. 8 2 Low Power Design Essentials Multiple Supply Voltages Block-level supply assignment – – – § – Higher throughput/lower latency functions are implemented in higher VDD Slower functions are implemented with lower VDD This leads to so-called “voltage islands” with separate supply grids Level conversion performed at block boundaries § Multiple supplies inside a block – – – Non-critical paths moved to lower supply voltage Level conversion within the block Physical design challenging Low Power Design Essentials 4. Using Three VDD’s © IEEE 2002 1.4 1 1 .4 1 .3 Power Reduction Ratio V3 (V ) 0 . 9 0 . 8 0 . 7 0 . 6 0 . 5 0 . 1 4 . 5 1.2 1 1 .2 1 .1 1 V 2 (V ) 0 .9 0 .8 0 .7 0 .6 V3 (V) 0.8 0.6 + 0 .5 0 .4 1 0 . 5 00 0. 5 V2 (V) 1 1. 5 0.4 0.4 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1 V 1 (V ) 1 .1 1 .2 1 .3 1 .4 0.6 0.8 1 1.2 1.4 V2 (V) V1 = 1.5V, VTH = 0.3V Low Power Design Essentials [Ref: T. Kuroda, 4. Optimum Number of VDD’s 1 . 0 { V1, V2 } V2 /V 1 { V1, V2, V3 } V2/ V1 V3/ V1 { V1, V2, V3, V4 } V2/ V1 V3/ V1 V4/ V1 VDD Ratio 0 . 5 1 . 0 P2 /P 1 © IEEE 2001 P Ratio P3/ P1 0 . 4 P4/ P1 § § § 0 . 5 (V) The more VDD’s the less power, but the effect saturates Power reduction effect decreases with scaling of VDD Optimum V2/V1 is around 0.7 [Ref: M. Hamada, CICC’01] 1 .1 V 0V) ( 1 . 5 0. 5 1. 01 V 1. 5 0. 5 1. 01 V 1. 5 (V) Low Power Design Essentials 4. Lessons: Multiple Supply Voltages § Two supply voltages per block are optimal Optimal ratio between the supply voltages is 0.7 Level conversion is performed on the voltage boundary, using a level-converting flip-flop (LCFF) An option is to use an asynchronous level converter – § § § More sensitive to coupling and supply noise Low Power Design Essentials 4. Distributing Multiple Supply Voltages Conventional VDD H i1 o1 VD DL i2 o2 VDD H VD DL i1 Shared N-well o1 i2 o2 VS S VDDH circuit Low Power Design Essentials VS S VDDL circuit VDDH circuit VDDL circuit 4. Conventional VDDL Row VDDH Row VDDL Row VDDH Row (a) Dedicated row VDD H N-well isolation VD DL VS S VDDH circuit Low Power Design Essentials VDDL circuit VDDH Region VDDL Region (b) Dedicated region 4. Shared N-Well VDDL circuit VDDH circuit Shared N-well VDD H VD DL VS S VDDH circuit VDDL circuit (a) Floor plan image 4. [Shimazaki et al, ISSCC’03] Low Power Design Essentials Example: Multiple Supplies in a Block Conventional Design F F F F F F F F F F F F F F F F F F F F FF FF FF FF FF © IEEE 1998 CVS Structure FF Level-Shifting F/F FF FF FF FF FF Critical Path Lower VDD portion is shared “Clustered voltage scaling” [Ref: M. Takahashi, ISSCC’98] Critical Path Low Power Design Essentials 4. Level Converting Flip-Flops (LCFFs) level conversion level conversion ckb d mf ck ck mo sf so q d db ck sf so q (inv.) MN1 MN2 ckb clk ck clk ck Pulsed HalfMasterLatch Slave Pulsed Half-Latch versus Master-Slave LCFFs § § § © IEEE 2003 Smaller # of MOSFETs / clock loading Faster level conversion using half-latch structure Shorter D-Q path from pulsed circuit [Ref: F. Ishihara, 4. Low Power Design Essentials Dynamic Realization of Pulsed LCFF § Pulsed precharge LCFF (PPR) – – – Fast level conversion by precharge mechanism Suppressed charge/discharge toggle by conditional capture Short D-Q path Pulsed Precharge Latch © IEEE 2003 Low Power Design Essentials [Ref: F. Ishihara, 4. Case Study: ALU for 64-bit µ Processor clock gen. clk 9:1 MUX INV2 9:1 MUX ain0 5:1 MUX 2:1 MUX bin : VDDH circuit : VDDL circuit Low Power Design Essentials ain gp gen. carry gen. partial sum logical unit carry sum sel. sum INV1 0.5pF s0/s1 sumb (long loop-back bus) © IEEE 2003 [Ref: Y. Shimazaki, 4. Low-Swing Bus and Level Converter VDD H pc VD DL sum INV1 sumb VD DL INV2 domino level converter (9:1 MUX) © IEEE 2003 § § VDD keeper H ain0 sel (VDD H) INV2 is placed near 9:1 MUX to increase noise immunity Level conversion is done by a domino 9:1 MUX [Ref: Y. Shimazaki, 4. Low Power Design Essentials Measured Results: Energy and Delay 8 © IEEE 2003 1.16G 0 7 Hz VDDL=1.4V 0 0 Energy:6 0 25.3% 0 5 Delay : 0 0 VDDL=1.2V +2.8% 4 0 Energy:0 3 33.3% 0 0 Delay : 2 0 0 +8.3% 1 0 1 1 1 0 . . . . TCYCLE . 0. 6 8 4 6 [0 ns] 2 [Ref: Y. Shimazaki, Room temperature Singlesupply Shared (VDDH=1. well 8V) Low Power Design Essentials Energy [pJ] 4. Practical Transistor Sizing § § § Continuous sizing of transistors only an option in custom design In ASIC design flows, options set by available library Discrete sizing options made possible in standard-cell design methodology by providing multiple options for the same cell – – Leads to larger libraries (> 800 cells) Easily integrated into technology mapping Low Power Design Essentials 4. Technology Mapping a b f c d slack=1 Larger gates reduce capacitance, but are slower Low Power Design Essentials 4. Technology Mapping Example: 4-input AND § § (a) Implemented using 4 input NAND + INV (b) Implemented using 2 input NAND + 2-input NOR Library 1: High-Speed Library 2: Low-Power Gate type INV NAND2 NAND4 NOR2 Area (cell unit) 3 4 5 3 Input cap. (fF) 1.8 2.0 2.0 2.2 Average delay (ps) 7.0 + 3.8 CL 10.3 + 5.3 CL 13.6 + 5.8 CL 10.7 + 5.4 CL Average delay (ps) 12.0 + 6.0 CL 16.3 + 8.8 CL 22.7 + 10.2 CL 16.7 + 8.9 CL (delay formula: CL in fF) Low Power Design Essentials (numbers calibrated for 90 nm) 4. Technology Mapping – Example 4-input AND Area HS: Delay (ps) LP: Delay (ps) Sw Energy (fF) § (a) NAND4 + INV 8 31.0 + 3.8 CL 53.1 + 6.0 CL 0.1 + 0.06 CL (b) NAND2 + NOR2 11 32.7 + 5.4 CL 52.4 + 8.9 CL 0.83 + 0.06 CL Area – – – – § Timing 4-input more compact than 2-input (2 gates vs. 3 gates) both implementations are 2-stage realizations 2nd stage INV (a) is better driver than NOR2 (b) For more complex blocks, simpler gates will show better performance Internal switching increases energy in the 2-input case Low-power library has worse delay, but lower leakage (see later) § Energy – – Low Power Design Essentials 4. Gate-Level Tradeoffs for Power § § Technology mapping § Gate selection § Sizing § Pin assignment Logical Optimizations § Factoring § Restructuring Buffer insertion/deletion Don’t care optimization 4. § § Low Power Design Essentials Logic Restructuring 1 1 0 1 0 1 0 1 1 Logic restructuring to minimize spurious transitions 1 1 1 1 2 1 3 1 1 1 1 Buffer insertion for path balancing Low Power Design Essentials 4. Algebraic Transformations Idea: Modify network to reduce capacitance p1=0.0 5 p3=0.07 5 f p2=0.0 5 p5=0.07 5 f p4=0.7 5 a b a c a b c pa = 0.1; pb = 0.5; pc = 0.5 Caveat: This may increase activity! Low Power Design Essentials 4. Lessons from Circuit Optimization § Joint optimization over multiple design parameters possible using sensitivity-based optimization framework – Equal marginal costs ⇔ Energy-efficient design § Peak performance is VERY power inefficient – – About 70% energy reduction for 20% delay penalty Additional variables for higher energy-efficiency § Two supply voltages in general sufficient; 3 or more supply voltages only offer small advantage Choice between sizing and supply voltage parameters depends upon circuit topology But … leakage not considered so far 4. § § Low Power Design Essentials Considering Leakage @ Design Time § § Considering leakage as well as dynamic power is essential in sub-100 nm technologies Leakage is not essentially a bad thing – – Increased leakage leads to improved performance, allowing for lower supply voltages Again a trade-off issue … Low Power Design Essentials 4. Leakage – Not Necessarily a Bad Thing 1 0. 8 0. 6 0. 4 0. 2 0 1 0 © IEEE 2004 Version 1 Vr t e m h 180m f 0.81 D ax VV D ( ELk ESw ) opt = 2 L ln d α avg −K n or m Version 2 E V tr e m h f 0.5 140m D a 2V V D x Topolog y (ELk/ES w)opt 0 In v Ad d De c 0. 0.5 0.2 8 2 11 0 Est ati c - 1 / dyna0 E mic 1 0 1 Optimal designs have high leakage (ELk/ESw ≈ 0.5) Must adapt to process and activity variations Low Power Design Essentials [Ref: D. Markovic, JSSC’04] 4. Refining the Optimization Model § Switching energy Obj116 § Leakage energy Obj117 with: I0(Ψ): normalized leakage current with inputs in state Ψ Low Power Design Essentials 4. Reducing Leakage @ Design Time § Using longer transistors – – Limited benefit Increase in active current Channel doping Stacked devices Body biasing § Using higher thresholds – – – § Reducing the voltage!! Low Power Design Essentials 4. Longer Channels 1 . 0 0 . 9 0 . 8 0 . 7 0 . 6 0 . 5 0 . 4 0 . 3 0 . 2 0 . 1 § 90 nm CMOS 1 0 9 Normalized leakage power Normalized switching energy 8 § Leakage power 7 6 5 § Switching energy 4 3 2 1 2 0 0 10% longer gates reduce leakage by 50% Increases switching power by 18% with W/L = const. 1 0 0 1 1 0 1 2 0 1 3 0 Doubling L reduces leakage by 5x § Impacts performance – 1 1 1 4 5 6 Transistor length 0 0 0 (nm) 1 7 0 1 8 0 1 9 0 Attractive when don’t have to increase W (e.g. memory) Low Power Design Essentials 4. Using Multiple Thresholds § There is no need for level conversion Dual thresholds can be added to standard design flows – § – – High-VTh and Low-VTh libraries are a standard in sub-0.18 m processes For example: can synthesize using only high-VTh and then only in-place swap in low-VTh cells to improve timing. Second VTh insertion can be combined with resizing § Only two thresholds are needed per block – Using more than two yields small improvements Low Power Design Essentials 4. Three VTH’s © IEEE 2002 1.4 1 .4 Leakage Reduction Ratio 1 1.2 1 .3 1 .2 1 .1 2 ( T H. V) 0 . 8 0 . 6 0 . 4 0 . 2 0 1 .1 5 V 1 1 V t h 1 (V ) 0 .9 0 .8 0 .7 0 .6 VTH.2 (V) 1. 5 0.8 0.6 0 .5 0 .4 0 . 5 00 0. TH.3 5V 1 0.4 0.4 + 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1 V t h 2 (V ) 1 .1 1 .2 1 .3 1 .4 (V) 0.6 0.8 1 1.2 1.4 VDD = 1.5V, VTH.1 = 0.3V Impact of third threshold very limited VTH.3 (V) Low Power Design Essentials [Ref: T. Kuroda, 4. Using Multiple Thresholds § § Cell-by-cell VTH assignment (not at block level) Achieves all-low-VTH performance with substantial leakage reduction in leakage FF FF FF FF FF High VTH Low Power Design Essentials Low VTH [Ref: S. Date, SLPE’94] 4. Dual-VT Domino Low-threshold transistors used only in critical paths Inv 2 Clk n P 1 Inv 3 Clkn+ 1 Dn+ 1 D n … Inv 1 Shaded transistors are low threshold 4. Low Power Design Essentials Multiple Thresholds and Design Methodology § Easily introduced in standard cell design methodology by extending cell libraries with cells with different thresholds – – – Selection of cells during technology mapping No impact on dynamic power No interface issues (as was the case with multiple VDD’s) Low Power Design Essentials 4. Dual-VTH Design for High-Performance Design High-VTH Only Total Slack Dynamic Power Static Power -53 psec 3.2 mW 914 nW Low-VTH Only 0 psec 3.3 mW 3873 nW Dual VTH 0 psec 3.2 mW 1519 nW All designs synthesized automatically using Synopsys Flows Low Power Design Essentials [Courtesy: Synopsys, Toshiba, 4. Example: High- vs. Low-Threshold Libraries 12 10 8 6 4 2 0 Selected combinational tests 130 nm CMOS Low Power Design Essentials Leakage Power (nW) [Courtesy: Synopsys 2004] 4. Complex Gates Increase Ion/Ioff Ratio 3 2 . 5 2 (90nm technology) No stack 1 4 0 1 2 0 1 (90nm technology) Ioff (nA) 1 . 5 1 0 . 5 0 Ion (µ Α) 0 6 0 4 0 2 0 0 08 No stack Stack 0 0 . 1 0 . 2 0 . 3 0 . 4 0 0 . VDD .6 5 0 . 7 0 . 8 0 . 9 1 Stack 0 0 . 1 0 . 2 0 . 3 0 . 4 0 0 . VDD .6 5 0 . 7 0 . 8 0 . 9 1 0 (V) (V) § § Ion and Ioff of single NMOS versus stack of 10 NMOS transistors Transistors in stack are sized up to give similar drive 4. Low Power Design Essentials Complex Gates Increase Ion/Ioff Ratio 3 . 5 3 2 . 5 2 1 . 5 1 x 10 5 (90nm technology) Stack Ion/Ioff ratio Factor 10! No stack 0 . 5 0 0 Stacking transistors suppresses submicron effects § Reduced velocity saturation § Reduced DIBL effect § Allows for operation at lower thresholds Low Power Design Essentials 4. 0 . 1 0 . 2 0 . 3 0 0 0 . VDD . . 4 (V) 5 6 0 . 7 0 . 8 0 . 9 1 Complex Gates Increase Ion/Ioff Ratio § Example: 4-input NAND versus Fan-in (4) Fan-in (2) 1 4 1 2 1 0 8 6 4 2 0 With transistors sized for similar performance: Leakage of Fan-in(2) = Leakage of Fan-in(4) x 3 (Averaged over all possible input patterns) Leakage Current (nA) Fan-in (2) Fan-in (4) 2 4 6 8 Low Power Design Essentials Input pattern 1 0 1 2 1 4 1 6 4. Example: 32 bit Kogge-Stone Adder factor 18 © Springer 2001 % of input vectors Standby leakage current (µ A) Reducing the threshold by 150 mV increases leakage of single NMOS transistor by factor 60 Low Power Design Essentials [Ref: S.Narendra, ISLPED’01] 4. Summary § § § § § Circuit optimization can lead to substantial energy reduction at limited performance loss Energy-delay plots the perfect mechanisms for analyzing energy-delay trade-off’s. Well-defined optimization problem over W, VDD and VTH parameters Increasingly better support by today’s CAD flows Observe: leakage is not necessarily bad – if appropriately managed. Low Power Design Essentials 4. References Books: § § § § § A. Bellaouar, M.I Elmasry, Low-Power Digital VLSI Design Circuits and Systems, Kluwer Academic Publishers, 1st Ed, 1995. D. Chinnery, K. Keutzer, Closing the Gap Between ASIC and Custom, Springer, 2002. D. Chinnery, K. Keutzer, Closing the Power Gap Between ASIC and Custom, Springer, 2007. J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed, Prentice Hall 2003. I. Sutherland, B. Sproul, D. Harris, Logical Effort: Designing Fast CMOS Circuits, MorganKaufmann, 1st Ed, 1999. Articles: § § § § § § R.W. Brodersen, M.A. Horowitz, D. Markovic, B. Nikolic, V. Stojanovic, “Methods for True Power Minimization,” Int. Conf. on Computer-Aided Design (ICCAD), pp. 35-42, Nov. 2002. S. Date, N. Shibata, S.Mutoh, and J. Yamada, "IV 30MHz Memory-Macrocell-Circuit Technology with a 0.5urn Multi-Threshold CMOS," Proceedings of the 1994 Symposium on Low Power Electronics, San Diego, CA, pp. 90-91, Oct. 1994. M. Hamada, Y. Ootaguro, T. Kuroda, “Utilizing Surplus Timing for Power Reduction,” IEEE Custom Integrated Circuits Conf., (CICC), pp. 89-92, Sept. 2001. F. Ishihara, F. Sheikh, B. Nikolic, “Level conversion for dual-supply systems,” Int. Conf. Low Power Electronics and Design, (ISLPED), pp. 164-167, Aug. 2003. P.M. Kogge and H.S. Stone, “A Parallel Algorithm for the Efficient Solution of General Class of Recurrence Equations,” IEEE Trans. Comput., vol. C-22, no. 8, pp. 786-793, Aug 1973. T. Kuroda, “Optimization and control of VDD and VTH for low-power, high-speed CMOS design,” Proceedings ICCAD 2002, pp. , San Jose, Nov. 2002. Low Power Design Essentials 4. References Articles (cont.): § § § § § § § § § H.C. Lin and L.W. Linholm, “An Optimized Output Stage for MOS Integrated Circuits,” IEEE J. Solid-State Circuits, vol. SC-10, no. 2, pp. 106-109, Apr. 1975. S. Ma and P. Franzon, “Energy Control and Accurate Delay Estimation in the Design of CMOS Buffers,” IEEE J. Solid-State Circuits, vol. 29, no. 9, pp. 1150-1153, Sept. 1994. D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, “Methods for True Energy-Performance Optimization,” IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, Aug. 2004. MathWorks, http://www.mathworks.com S. Narendra, S. Borkar, V. De, D. Antoniadis, A. Chandrakasan, “Scaling of stack effect and its applications for leakage reduction,” Int. Conf. Low Power Electronics and Design, (ISLPED), pp. 195-200, Aug. 2001. T. Sakurai and R. Newton, “Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990. Y. Shimazaki, R. Zlatanovici, B. Nikolic, “A shared-well dual-supply-voltage 64-bit ALU,” Int. Conf. Solid-State Circuits, (ISSCC), pp. 104-105, Feb. 2003. V. Stojanovic, D. Markovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, “Energy-Delay Tradeoffs in Combinational Logic using Gate Sizing and Supply Voltage Optimization,” European SolidState Circuits Conf., (ESSCIRC), pp. 211-214, Sept. 2002. M. Takahashi et al., “A 60mW MPEG video codec using clustered voltage scaling with variable supply-voltage scheme,” IEEE Int. Solid-State Circuits Conf., (ISSCC), pp. 36-37, Feb. 1998. Low Power Design Essentials 4. ...
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Ch4_DT-Circuits - Optimizing Power @ Design Time Circuits...

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