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Ch4_DT-Circuits - Optimizing Power Design Time Circuits Jan...

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Low Power Design Essentials ©2008 4.1 Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 4 Optimizing Power @ Design Time Circuits Dejan Marković Borivoje Nikolić
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Low Power Design Essentials ©2008 4.2 Chapter Outline § Optimization framework for energy-delay trade-off § Dynamic power optimization Multiple supply voltages Transistor sizing Technology mapping § Static power optimization Multiple thresholds Transistor stacking
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Low Power Design Essentials ©2008 4.3 Energy/Power Optimization Strategy § For given function and activity, an optimal operation point can be derived in the energy-performance space § Time of optimization depends upon activity profile § Different optimizations apply to active and static power Fixed Activity Variable Activity No Activity - Standby Active Design time Run time Sleep Static
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Low Power Design Essentials ©2008 4.4 Maximize throughput for given energy or Minimize energy for given throughput Delay Unoptimized design Obj100 Em ax Dm ax Dmi n Energy/op Emi n Energy-Delay Optimization and Trade-off Trade-off space Other important metrics: Area, Reliability, Reusability
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Low Power Design Essentials ©2008 4.5 The Design Abstraction Stack Logic/RT (Micro-)Architecture Software Circuit Device System/Application This Chapter A very rich set of design parameters to consider! It helps to consider options in relation to their abstraction layer sizing, supply, thresholds logic family, standard cell versus custom Parallel versus pipelined, general purpose versus application specific Bulk versus SOI Choice of algorithm Amount of concurrency
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Low Power Design Essentials ©2008 4.6 Architecture Micro-Architecture Circuit (Logic & FFs) Optimization Can/Must Span Multiple Levels Design optimization combines top-down and bottom-up: “meet-in-the-middle”
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Low Power Design Essentials ©2008 4.7 Obj101 topology A Delay Energy/op Globally optimal energy-delay curve for a given function Energy-Delay Optimization topology B Obj102 topology A topology B Delay Energy/op
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Low Power Design Essentials ©2008 4.8 Some Optimization Observations ∂E / ∂A ∂D / ∂A A= A0 SA = S B S A f (A0,B) f (A,B0) Delay Energy D 0 (A0,B0 ) Energy-Delay Sensitivities [Ref: V. Stojanovic, ESSCIRC’02 ]
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Low Power Design Essentials ©2008 4.9 ∆E = SA∙( ∆D) + SB∙∆D On the optimal curve, all sensitivities must be equal Finding the Optimal Energy-Delay Curve f (A0,B) f (A,B0) Delay Energy D 0 (A0,B 0) ∆D f (A1,B) Pareto-optimal: the best that can be achieved without disadvantaging at least one metric.
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Low Power Design Essentials ©2008 4. 10 § Reducing voltages Lowering the supply voltage ( VDD ) at the expense of clock speed Lowering the logic swing ( Vswing ) § Reducing transistor sizes ( CL ) Slows down logic § Reducing activity ( α ) Reducing switching activity through transformations Reducing glitching by balancing logic f V V C P DD swing L active α ~ DD swing L active V V C E α ~ Reducing Active Energy @ Design Time
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Low Power Design Essentials ©2008 4.
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