Ch5_DT-Architecture

Ch5_DT-Architecture - Low Power Design Essentials 5.1 Jan...

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Unformatted text preview: Low Power Design Essentials 5.1 Jan M. Rabaey Dejan Markovi Low Power Design Essentials 2008 Chapter 5 Optimizing Power @ Design Time Architectures, Algorithms and Systems Low Power Design Essentials 5.2 Chapter Outline The architecture/system trade-off space Concurrency improves energy-efficiency Exploring alternative topologies Removing inefficiency The cost of flexibility Low Power Design Essentials 5.3 Motivation Optimizations at the architecture or system level can enable more effective power minimization at the circuit level (while maintaining performance), such as Enabling a reduction in supply voltage Reducing the effective switching capacitance for a given function (physical capacitance, activity) Reducing the switching rates Reducing leakage Optimizations at higher abstraction levels tend to have greater potential impact While circuit techniques may yield improvements in the 10-50% range, architecture and algorithm optimizations have reported orders of magnitude power reduction Low Power Design Essentials 5.4 [Ref: D. Markovic, JSSC04] Circuit Optimization Limited in Range Case study: Tree adder Result of joint ( VDD , VTH , W ) optimization: 65% of energy saved without delay penalty 25% smaller delay without energy cost Need higher level optimizations for larger gain Lessons Learned from Circuit Optimization D/Dr ef E/Er ef 0.5 1 1.5 1.5 1 0.5 65% ref Ref : min delay @ nominal Vdd, Vth 25% Low Power Design Essentials 5.5 Logic/RT (Micro-)Architecture Software Circuit Device System/Application Increasing Return-on-Investment (ROI) at higher levels of the stack Chapter 4 The Design Abstraction Stack Low Power Design Essentials 5.6 Removing inefficiencies (1) Discrete options (3) Alternative topologies (2) D E D E D E Architecture and system transformations and optimizations reshape the E-D curves Expanding the Playing Field Low Power Design Essentials 5.7 (while maintaining performance) Concurrency: trading off clock frequency versus area to reduce power F1 Consider the following reference design F2 R R R fre f R: register, F1,F2: combinational logic blocks (adders, ALUs, etc) Cref : average switching capacitance [A. Chandrakasan, JSSC92] Reducing the Supply Voltage Low Power Design Essentials 5.8 F1 F2 R R R fref /2 F1 F2 R R R fref /2 Running slower reduces required supply voltage Yields quadratic reduction in power Almost cancels A Parallel Implementation Low Power Design Essentials 5.9 Assuming ovpar = 7.5% Example: 90nm Technology . 5 . 6 . 7 . 8 . 9 1 1 1 . 5 2 2 . 5 3 3 . 5 4 4 . 5 5 VDD (norm.) tp (norm. ) Low Power Design Essentials 5. F1 F2 R R R fre f R R fre f Assuming ovpipe = 10% Shallower logic reduces required supply voltage A Pipelined Implementation (this example assumes equal Vdd for par / pipe designs) Low Power Design Essentials 5....
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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Ch5_DT-Architecture - Low Power Design Essentials 5.1 Jan...

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