Ch6_DT-Interconnect

Ch6_DT-Interconnect - Low Power Design Essentials 6.1 Jan...

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Unformatted text preview: Low Power Design Essentials 6.1 Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 6 Optimizing Power @ Design Time Interconnect and Clocks Low Power Design Essentials 6.2 Chapter Outline § Trends and bounds § An OSI approach to interconnect optimization – Physical layer – Data link and MAC – Network – Application § Clock distribution Low Power Design Essentials 6.3 ITRS Projections Calendar Year 2012 2018 2020 Interconnect One Half Pitch 35 nm 18 nm 14 nm MOSFET Physical Gate Length 14 nm 7 nm 6 nm Number of Interconnect Levels 12-16 14-18 14-18 On-Chip Local Clock 20 GHz 53 GHz 73 GHz Chip-to-Board Clock 15 GHz 56 GHz 89 GHz # of Hi Perf. ASIC Signal I/O Pads 2500 3100 3100 # of Hi Perf. ASIC Power/Ground Pads 2500 3100 3100 Supply Voltage 0.7-0.9 V 0.5-0.7 V 0.5-0.7 V Supply Current 283-220 A 396-283 A 396-283 A [Source: ITRS Roadmap, 2004, 2005] Low Power Design Essentials 6.4 Increasing Impact of Interconnect § Interconnect is now exceeding transistors in – Latency – Power dissipation – Manufacturing complexity § Direct consequence of scaling Low Power Design Essentials 6.5 Communication Dominant Part of Power Budget 65 % 21 % 9 % 5 % Interconnec t Cloc k I/ O CL B FPG A μ Process or Signal processor Cloc k Logi c Memor y I/ O ASSP Cloc ks Cach es Executio n Uni ts Contr ol I/O Drivers 40 % 20 % 15 % 15 % 10 % Low Power Design Essentials 6.6 Idealized Wire Scaling Model Parameter Relation Local Wire Constant Length Global Wire W, H, t 1/ S 1/ S 1/ S L 1/ S 1 1/ SC C LW/t 1/ S 1 1/ SC R L / WH S S 2 S 2/SC tp ~ CR L 2/ Ht 1 S 2 S 2/SC2 E CV 2 1/ SU 2 1/ U 2 1/( SCU 2) Low Power Design Essentials 6.7 Distribution of Wire Lengths on Chip [Ref: J. Davis, C&S’98] © IEEE 1998 Picture 7 Low Power Design Essentials 6.8 Technology Innovations Reduce dielectric permittivity (e.g. Aerogels or air) Reduce resistivity (e.g. Copper) Reduce wirelengths through 3D-integration Novel interconnect media (carbon nanotubes, optical) (Pictures courtesy of IBM and IFC FCRP) © IEEE 1998 Low Power Design Essentials 6.9 Logic Scaling 1-1 2 1-9 1-6 1-3 1 P t p ~1/ S 3 1 1-3 1-6 1-9 1-1 2 1-1 5 Power [W], P Delay [s], tp 1-6 J 1-9 J 1-1 2 J 1-1 5 J 1-1 8 J [Ref: J. Davis, Proc’01] Low Power Design Essentials 6. Interconnect Scaling Delay [s], τ (Length)-2 [cm-2], L-2 (Length) [cm], L 1-1 8 1-1 5-1 2 1-9 1-6-3 L-2 τ = 10-5 [s/cm-2] (F = 0.1µ ) L τ ~ S 2 1 8 6 4 2-2-4-5-4-3-2-1-2 1-1 3 (1 00 0µ ) -1 1 (1 µ) 1-9 ( 1 µ ) 1-7 ( 1 µ ) [Ref: J. Davis, Proc’01] Low Power Design Essentials 6. Lower Bounds on Interconnect Energy Claude Shannon ) 1 ( 2 log kTB P B C S + ≤ C: capacity in bits/sec B: bandwidth Ps: average signal power C P E S bit / = Valid for an “infinitely long” bit transition (C/B→0) Equals 4.10-21J/bit at room temperature ) 2 ln( ) / ( (min) kT B C E E bit bit = → = Shannon’s theorem on maximum capacity of communication channel [Ref: J. Davis, Proc’01] Low Power Design Essentials 6....
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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Ch6_DT-Interconnect - Low Power Design Essentials 6.1 Jan...

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