Ch9_SB-Memory

Ch9_SB-Memory - Optimizing Power @ Standby Memory Benton H....

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Low Power Design Essentials 9.1 Benton H. Calhoun Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 9 Optimizing Power @ Standby Memory
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Low Power Design Essentials 9.2 Chapter Outline § Memory in Standby § Voltage Scaling § Body Biasing § Periphery
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Low Power Design Essentials 9.3 Memory Dominates Processor Area § SRAM is a major source of static power in ICs, especially for low power applications § Special memory requirement: need to retain state in standby § Metrics for standby: 1. Leakage power 2. Energy overhead for entering/leaving standby 3. Timing/area overhead B L B L W L M1 M2 M3 M4 M5 M6 Q QB
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Low Power Design Essentials 9.4 Reminder of “Design Time” Leakage Reduction § Design-time techniques (Ch 7) also impact leakage High VTH transistors Different precharge voltages Floating BLs § This Chapter: adaptive methods that uniquely address memory standby power
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Low Power Design Essentials 9.5 The Voltage Knobs § Changing internal voltages has different impact on leakage of various transistors in [Ref: Y. Nakagome, IBM’03] Offset voltage, B   (V) Leakage reduction (ratio) 1 1 0 - 1 1 0 - 2 1 0 - 3 1 0 - 4 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 0 - 5 L = 90 nm, tOX = 2 nm VDD = 1 V S = 100 mV/decade   K = 0.2 V1/2, 2B   = 0.6 V B   = 0.05 V D D 0 0 - V D D 0 0 - V D D + 0 VD - 0 0 0 (DIBL ) NM OS V D D 0 0 + C B 1 B 2 A 1 A 2 δ - 2245 TH V ) 2 2 ( ψ - + 2245 k V TH
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Low Power Design Essentials 9.6 Lower VDD in Standby § Basic Idea: Lower VDD lowers leakage sub-threshold leakage GIDL gate tunneling § Question: What sets the lower limit? [Ref: K. Flautner, ISCA VD D VDDl ow VDD _S RAM drowsy drowsy SRAM VD D VDD H VD DL Active mode Standby mode Example
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Low Power Design Essentials 9.7 Limits to VDD Scaling: DRV Data Retention Voltage (DRV): Voltage below which a bitcell loses its data That is, the supply voltage at which the Static Noise Margin (SNM) of the SRAM cell in standby mode reduces to zero . [Ref: H. Qin, ISQED ’04] 1 0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4 V ( V 2 ( ) VTC 1 VTC 2 V D D =0.18V V D D =0.4V 130 nm CMOS
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Low Power Design Essentials 9.8 Power savings of DRV 0 0 . 6 0 . 8 1 0 1 0 2 0 3 0 4 0 5 0 6 0 Supply Voltage (V) Leakage Current (A) μ Meas ured DRV range More than 90% reduction in leakage power with 350mV standby VDD (100mV guard band). Test chip in 130 nm CMOS technology with built-in voltage regulator 1.4 mm 1.4 mm IP Module of 4kB SRAM [Ref: H. Qin, ISQED’04]
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Low Power Design Essentials 9.9 DRV and Transistor Sizes 0 1 2 3 140 150 160 170 180 190 Width Scaling Factor DRV (mV) M a M p M n Model With Ma , Mp and Mn the access transistor, PMOS pull-up and NMOS pull-down, respectively [Ref: H. Qin, Jolpe ’06]
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9. Impact of Process “Balance”
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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Ch9_SB-Memory - Optimizing Power @ Standby Memory Benton H....

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