0 25 self adjusting threshold voltage scheme sats

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Unformatted text preview: are 13%) and 55%, respectively Low Power Design Essentials 10. 0.0 05 0. 0 1 0.0 15 0. 0 2 0.0 25 Self-Adjusting Threshold Voltage Scheme (SATS) Leakage Sensor ON/OFF Well-Bias Circuit Vwell VD D VD D ON/OFF Vw ell V G Low VTH → large leakage → SSB ON → VBB↓ → High VTH High VTH → little leakage → SSB OFF → VBB↑ → Low VTH Low Power Design Essentials [Ref: T. Kobayashi, CICC94] 10. SATS Experimental Results © IEEE 1994 Low Power Design Essentials [Ref: T. Kobayashi, 10. Adaptive Body Bias ─ Experiment Multiple subsites 5.3 mm PD & Counter Resistor Network 4.5 mm Delay Resistor Network CUT Bias Amplifier © IEEE 2002 Technology # of subsites per die Subsite size Body bias range Bias resolution 150 nm CMOS 21 1.6 x 0.24 mm 0.5V FBB to 0.5V RBB 32 mV [Ref: J. Tschanz, 10. Low Power Design Essentials Adaptive Body Bias ─ Results t o le o ak y Number of dies t o sl o o w f ta rg et A B B F B B Frequen cy within die ABB RB B f tar get noBB 10 0% ABB 97% highest bin 100% yield Accepted die 6 0 % 2 0 %0 % For given frequency and power density • 100% yield with DBB • 97% highest freq bin with ABB for within die variability Low Power Design Essentials low frequency bin high frequency bin [Ref: J. Tschanz, 10. Advantage of Adaptive Biasing at Low VDD/VTH 5 0 4 5 4 0 Eswitching (fJ) 3 5 3 0 2 5 2 0 1 5 0 Adaptive Tuning Worst Case, w/o Vth tuning Worst Case, w/ Vth tuning Nominal, w/o Vth tuning Nominal, w/ Vth tuning 12 x VDD: 200-500mV 1 5 1.0E+ 03 1.0E+ 04 1.0E+ 05 1.0E+ 06 1.0E+ 07 Path Delay (ps) VTH tuning allows operation at nominal conditions Low Power Design Essentials [Courtesy: K. Cao, 10. Combining DVS and ABB © IEEE 2002 Low Power Design Essentials [Ref: M. Miyazaki, ISSCC’02] 10. Adapting VDD and VTH 14 0 12 0 10 0 8 0 6 0 4 0 2 0 0 0 © IEEE 2002 180 nm CMOS Power (mW) Dynami c Voltage Scaling Adaptive Supply And Body Bias 1 0 2 3 0 0 Frequency 4 0 5 0 6 0 10. Low Power Design Essentials (MHz) [Ref: M. Miyazaki, ISSCC’02] Combining DVS and ABB © IEEE 2003 Low Power Design Essentials [Ref: T. Chen, 10. A Generalized Self-Adapting Approach Motivation: Most variations are systematic or slowly varying, and can be measured and adjusted for on a periodic base Parameters to be measured: temperature, delay, leakage • Parameters to be controlled: VDD, VTH (or VBB) • Sensors Tclo ck Controller VBB, VDD Module Achieves the maximum power saving under technology limit • Inherently improves the robustness of design timing • Minimum design overhead required over the traditional design methodology • Low Power Design Essentials 10. Aggressive Deployment (AD) § § Also known as “Better-than-worst-case (BTWC) design” Observation: – Current design targets worst case conditions, which are rarely encountered in actual operation Operate circuits at lower voltages level than allowed by worst case and deal with the occasional errors in other ways Example: Operate memory at voltages lower than allowed by worst case, and deal with the occasional errors through error-correction § Remedy: – Histogram of 32K SRAM cells 60 00 50 00 40 00 30 00 20 00 10 00 0 1 0...
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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