5v bulk cmos extended to embedded processors arm

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Unformatted text preview: 130nm 1.5V bulk-CMOS – § Pentium M: 130nm 1.5V bulk-CMOS – § Extended to embedded processors (ARM, Freescale, TI, Fujitsu, NEC, …) Low Power Design Essentials 10. DVS Challenge: Verification § Functional verification – Circuit design constraints Circuit delay variation Noise margin reduction Delay sensitivities (local power grid) § Timing verification – § Power distribution integrity – – Need to verify at every voltage operation point? Low Power Design Essentials 10. Design for Dynamically Varying VDD § Logic needs to be functional under varying VDD – Careful choice of logic styles is important (static versus dynamic, tristate busses, memory cells, sense amplifiers § Also: need to determine max |dVDD/ dt| Low Power Design Essentials 10. Static CMOS Logic VD D VD D In = 0 Vout = VDD CL RDS,P MOS Vo ut C L Static CMOS operates robustly with varying VDD Low Power Design Essentials 10. Dynamic Logic VD D clk clk = 1 Errors Vo ut Vi n clk Volt s VD D Vo ut Time • ∆ V False logic low: ∆ VDD > DD VTP Latch-up: ∆ VDD > − ∆ VD Vbe D Sets strong upper limit on |dVDD/dt| • Cannot gate clock in evaluation state. • Tri-state busses fail similarly x Use hold circuit. Low Power Design Essentials 10. DVS System Transient Response Ring oscillator ( for |dVDD/dt| = 20 V/µ sec) 4 3 2 1 0 6 0 8 0 10 0 12 0 0.6 µ m CMOS VD D fCL K 16 18 14 0 0 Time (ns) 0 20 0 22 0 24 0 26 0 Output fCLK instantaneously adapts to new VDD. Low Power Design Essentials [Ref: T. Burd, JSSC’00] 10. Relative Timing Variation Delay relative to ring oscillator +4 0 Percent Delay Variation Four extreme cases of critical paths: +2 0 0 Seri on es 4V 3V 2V VDD 2V TH TH TH 0T § Delay for all components varies monitonically with VDD H §Timing verification only needed at min & max VDD. Low Power Design Essentials [Ref: T. Burd, UCB’01] Gat e Ring Interconn oscillator ect Diffusi 10. Delay Sensitivity ∂Delay ∂Delay ∆VDD = ⋅ , Delay ∂VDD Delay (VDD ) 1 0 . 0 8 . 0 6 . 0 4 . 0 2 V 2 VDD 3 T V V § Sensitivity max at 2 VTH H T T § Local power grid only needs to be verified at VDD H H Normalized Delay / Delay Low Power Design Essentials ∆VDD = I (VDD ) ⋅ R 4 V T 2VTH H 10. [Ref: T. Burd, UVB’01] Adapative Body Biasing (ABB) § § § Similar to DVS, transistor thresholds can be varied dynamically during operation using body biasing Extension of DBB approach considered for standby leakage management Motivation: – – – – Extends dynamic E-D optimization scope (as a function of activity) Helps to manipulate and control leakage Helps to manage process and environmental variability (especially VTH variations) Is becoming especially important for low VDD/VTH ratios Low Power Design Essentials 10. Threshold Variability and Performance 1 . 4 1 . 3 VTHnom = 0.325V VDD = 0.45V VDD = 0.6V VDD = 1.V normalized delay 1 . 2 1 . 1 1 0 . 9 0 . 8 0 .0.02 7 5 0. 02 0.01 5 0. 01 0.00 5 90 nm CMOS ∆ (V 0 T H ) (V Delay variation at 1V and 0.45V...
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