Ch10_RT

# 9 dynamic voltage scaling dvs reduces dynamic

This preview shows page 1. Sign up to view the full content.

This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: r Design Essentials 10.9 Dynamic Voltage Scaling (DVS) Reduces Dynamic Energy/Operation Superlinearly 1 0 . 9 0 . 8 0 . 7 0 . 6 0 . 5 0 . 4 0 . 3 0 . 2 0 .0 1. 2 Nominal operation point (α=1.3, VDDnom/VTH = 4) normalized energy e 0 . 3 0 0 0 . . . 4 normalized 5 6 0 . 7 0 . 8 0 . 9 1 When performance is not needed, relax and save energy. Low Power Design Essentials 10. performance f Dynamic Voltage Scaling (DVS) Even more impressive when considering power 1 0 . 9 0 . 8 0 . 7 0 . 6 0 . 5 0 . 4 0 . 3 0 . 2 0 . 1 0 . 2 Nominal operation point (α =1.3, VDDnom/VTH = 4) normalized power p Third order reduction in power when scaling supply voltage with workload (for α = 2 and VDD &gt;&gt; VTH) 0 . 3 0 . 4 0 0 . . 5 6 normalized 0 . 7 0 . 8 0 . 9 1 performance f But … needs continuously variable supply voltage Low Power Design Essentials 10. Using Discrete Voltage Levels § § DVS needs close integration with voltage regulation Continuously variable supply voltage not always available 1 0 . 9 0 . 8 0 . 7 0 . 6 0 . 5 0 . 4 0 . 3 0 . 2 0 .0 1. 2 Nominal operation point (α=1.3, VDDnom/VTH = 4) normalized energy e Dithering supply voltage between discrete levels approximates continuous scaling VDDno m/2 0 . 3 0 0 0 . . . 4 normalized 5 6 0 . 7 0 . 8 0 . 9 1 performance f Low Power Design Essentials [Ref: V. Gutnik, Example: • Operate 50% of time at VDDnom, and 50% at VDDnom/2 • Reduces e to 0.625 for f = 0.74 • Continuous DVS would yield e ≈ 0.5 10. Challenge: Estimating the Workload § § § Adjusting supply voltage is not instantaneous and may take multiple clock cycles Efficiency of DVS strong function of accuracy in workload estimation Depending upon type of workload(s), their predictability and dynamism – – Stream-based computation General-purpose multi-processing Low Power Design Essentials 10. Example 1: Stream-based Processing § Examples: voice or multimedia processing Control VD D fcl k Stream in R E G FI F O Processor CLK F I F O R E G Stream out FIFO measures workload § Control dynamically adjusts VDD (and hence fclk) § Low Power Design Essentials [Ref: L. Nielsen, TVLSI’94] 10. Stream-based Processing and Voltage Dithering (also known as voltage hopping) MPEG-4 encoding Time #n #n+1 Normalized power 0. 8 0. 6 0. 4 0. 2 8 10. 1 Transition time between ƒ levels = 200µs Next milestone n-th slice finished here Two hopping levels are sufficient. 0 1 2 3 # of frequency levels Low Power Design Essentials [Ref: T. Sakurai, Relating VDD and fclk § Self-timed – – Avoids clock all-together Supply is set by close loop between VDD setting, processor speed, and FIFO occupation Closed loop compares desired and actual frequency Needs “dummy” critical path to estimate actual delay Stores relationship between fclk (processor speed) and VDD Obtained from simulations or calibration § On-Line Speed Estimation – – § Table-Look Up – – Low Power Design Essentials 10. On-Line Speed Estimation Batte ry DC/DC Frequency detector fre + Σ q - Loop Filter VD D Proc VCO factu al Simultaneously performs regulation and clock generation VCO sets clock frequency • Uses replica of critical path of processo...
View Full Document

Ask a homework question - tutors are online