Ch10_RT - Optimizing Power Runtime Circuits and Systems Jan...

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Low Power Design Essentials 10.1 Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 10 Optimizing Power @ Runtime Circuits and Systems
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Low Power Design Essentials 10.2 Chapter Outline § Motivation behind run-time optimization § Dynamic voltage and frequency scaling § Adaptive body biasing § General self-adaptation § Aggressive deployment § Power domains and power management
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Low Power Design Essentials 10.3 Why Run-Time Optimization for Power? § Power dissipation strong function of activity § In many applications, activity various strongly over time: Example 1: Operational load varies dramatically in general purpose computing. Some computations also requires faster response than others. Example 2: The amount of computation to be performed in many signal processing and communication functions (such as compression or filtering) is a function of the input data stream and its properties. . § Optimum operation point in the performance-energy space hence varies over time § Changes in manufacturing, environmental or aging conditions also lead to variable operation points Designs for a single fixed design point are sub-optimal
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Low Power Design Essentials 10.4 Variable Workload in Media Processing Example: Video Compression [Courtesy: A. Chandrakasan] Typical MPEG IDCT Histogram True also for voice processing, graphics, multimedia and communications
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Low Power Design Essentials 10.5 Variable Workloads in General-Purpose Computing [Ref: A. Sinha, VLSI’01] Workload traces of three processor styles over 60 sec’s Laptop CPU usage chart File server Workstation Dialup server
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Low Power Design Essentials 10.6 Adapting to Variable Workloads § Goal: Position design in optimal operational point given required throughput § Useful dynamic design parameters: VDD and VTH Changing transistor sizes dynamically non- trivial § Variable supply voltage most effective for dynamic power reduction
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Low Power Design Essentials 10.7 Adjusting Only the Clock Frequency § Often used in portable processors § Only reduces power – leaves energy/operation constant Does not save battery life Compute ASAP Delivered Throughput Clock Frequency Reduction Excess throug hput Always high throughput Energy/operation remains unchanged while throughput scales down with f CLK f CLK Redu ced time time [Ref: T. Burd, UCB’01]
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Low Power Design Essentials 10.8 Dynamic Voltage Scaling (DVS) time Matches execution speed to requirements Minimizes average energy/operation Extends battery life up to one order of magnitude with the exact same hardware! Vary VDD and f CLK based on requested throughput Delivered Throughput [Ref: T. Burd, UCB’01]
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Low Power Design Essentials 10.9 Flashback: VDD and Throughput 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 normalized performance f normalized supply v Nominal operation point ) 1 ( ) 1 ( v v v v f t t α - - = With f and v the throughput and supply voltage normalized to the nominal values, and vt the ratio between threshold and nominal supply voltages.
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Ch10_RT - Optimizing Power Runtime Circuits and Systems Jan...

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