This preview shows page 1. Sign up to view the full content.
Unformatted text preview: ply Voltage 1 % performance impact, 50 % energy reduction
Low Power Design Essentials [Ref: D. Ernst, Micro’03] 10. The Industrial Experience Under typical case conditions all chips are at least 39% more energy efficient - Worst-case design uses margins for corners that are very infrequent, or even impossible § Typical-case operation requires an understanding of when and how systems break!
§ Low Power Design Essentials [Courtesy: K. Flautner, ARM 10. Aggressive Deployment at the Algorithm Level
Main Block y a [ n]
>Th ˆ y[n] Estimator ye [ n]
Picture 38 § § § § Main Block aggressively scaled in voltage Error detection: Estimator provides upper and lower bounds for output y Error correction: Estimator bounds used when output of Main Block falls outside. Mostly applicable to signal processing and communication applications where Low Power Design Essentials [Ref: B. Shim, 10. Example: Motion Estimation for Video Compression
Up to 60% power savings using AD, 6X reduction in PSNR variance in presence of process variations error-free 23.95dB with errors 22.44 dB error-corrected 23.54 dB Low Power Design Essentials [Ref: G. Varatkar, 10. Other Better-Than-Worst-Case Strategies
© IEEE 2004 § Self-Tuning Circuits [Kehl93]
– – Early work on dynamic timing error avoidance Adaptive clock control § Time Based Transient Fault Detection [Anghel00]
– Double sampling latches for speed testing § § Going beyond worst-case specs with TEAtime [Uht00] On-Chip Self-Calibrating Communication IEEE Computer Magazine, March 2004.
Low Power Design Essentials 10. Power Domains (PDs)
Introduction of multiple voltage domains on single die creates extra challenges: § Need for multiple voltage regulators and/or voltage up-down converters § Reliable distribution of multiple supplies § Interface circuits between voltage domains § System-level management of domain modes
– Trade-off gains of changing power modes with overhead of doing so Low Power Design Essentials 10. Power Manager (PM)
Time subsystem Power N etwor k Power D omain A Power D omain B Power D omain C PIF PIF Agent PIF Agent PIF Agent PIF Power N etwork Interface Command/ Event Dispatcher Clock subsystem PIF Power subsystem PM: Centralizes power control Power subsystem – gates block power rails § Clock subsystem – gates block clocks § Timer subsystem – system time-wheel and wake-up timers Standardized interface (PIF) between PM and Power Domains
§ Low Power Design Essentials [Ref: M. Sheets, VLSI’06] 10. Managing the Timing
§ Basic scheduling schemes
§ § Sleep when not actively processing Wake up in response to a pending event Sleep if idle and probably not needed in near future [Simunic’02] Wake up due to expected event in the near future – Stochastic
§ § § Metrics
– – – Correctness – PD awake when required to be active Latency – time required to change modes Efficiency – minimum total energy consumption [Liao’02]
§ Minimum idle time – time required for savings in lower-power mode to offset...
View Full Document
This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.
- Spring '10