Interfacing between power domains separate internal

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Unformatted text preview: energy spent switching modes Eoverhead − Pidlet switch _ modes Elost Min. Idle Time = = Psavings Psleep − Pidle Low Power Design Essentials 10. Interfacing between Power Domains Separate internal logic of block from its interfaces 1. Communicate with other PDs by bundling related signaling into “ports” – – Communication through a port requires permission (session-based) Permission is obtained through power control interface Can force to a known value (e.g. the non-gated power rail) Can perform level conversion Port A Signal Block wall Power control interface !sleep In sleep Port B !open open Out sleep 2. Signal wall maintains interface regardless of power mode – – Signal wall Interface for block with two ports Low Power Design Essentials Example signal wall schematic (Port) 10. Example: PDs in Sensor Network Processor 2.7x2.7 mm2 (130 nm CMOS) Clock Rates Supply clk osc serial. volt if conv. 8 MHz – 80 KHz 0.3-1V 53 µ W 150 µ W 5 mW Leakage Power Average Power Peak Power 64kB code/data RAM location dw 8051 µP 1kB TX/RX queues DLL baseband PM neighbor 1200 RX listen windows TX broadcast packet Power (µ W) 766 © IEEE 2006 60 i basebf and ser ial neigh bor locat ion que ues dw8 051 d l l Low Power Design Essentials [Ref: M. Sheets, VLSI’06] Sleep signals 10. Integrated Switched-Capacitor Voltage Converter C l k C l k 10 pF 10 pF 10 pF 10 pF 10 pF C l k Rl o a d C C l k Equalizing C 1 V C l k C C C phase C Charging phase R l o a d C C C C Rl o a d 85% efficiency at 1V when optimized for load Output voltage ripple function of Rload and fClk Low Power Design Essentials [Ref: H. Qin, ISQED’04] 10. Integrated Power Converter for Sensor Networks Solar Cell Electromagnet icha S ker Piezoelectr icen B der Thermoelectr icenera G tor Ni C MH ell (1.2 V) LiI C on 3.6 ell ( V) Ultracapaci tor Microcontroller + sensors 1:2 converter Level shifters Microcontrol ler Ra dio Sens ors Mem ory 3:2 converter Integrated power manager Switched-capacitor converters operate at high-efficiency (up to 80%) at low current levels 10. Ra dio Low Power Design Essentials [Ref: M. Seeman, CICC’07] LC-based DC-DC (buck) converter VDD, High Voltage Controlle r Output filter LF RS VDD,INTE RNAL CF Load © IEEE 2006 Challenge: • Need good low-resistive L & high-capacitive C • Hard to achieve on-chip • Option: Use multi-chip stacking PA D 2m m C ap 1 n F [Ref: K. Onizuka, A10. Low Power Design Essentials Revisiting Power Distribution Concept § § Current On-Chip Power Distribution: Single metal grid extended with switches for power gating Need for: higher voltage distribution and integrated level converters and switches Hard to accomplish on standard integrated circuit Opportunities offered by stacked dies and 2.5D integration § Thicker wires, better inductors and capacitors Towards “PGE on a chip” § § § Low Power Design Essentials [Ref: J. Rabaey, 10. Revisiting Power Distribution L&C cell array Power supply & other wires Inductors Capacitors THV’s Interposer Sensor, MEMS, High voltage generation, Analog, RF etc. (3D stacke...
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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