Low power design essentials aggressive deployment

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 0 2 0 DRV 0 (mV) 3 0 0 4 0 0 Aggressive Deployment Distribution ensures that errorrate is low 10. Low Power Design Essentials Aggressive Deployment ─ Concepts § Probability of hitting tail of distribution at any time is small – Function of critical path distribution, input vectors and process variations Supply voltage set to worst case (+ margins) § Worst-case design expensive from energy perspective – § Aggressive deployments scales supply voltage below worst-case value – – “Better-than-worst-case” design strategy Uses error detection and correction techniques to handle rare failures Low Power Design Essentials 10. Aggressive Deployment ─ Components Must include the following components: § Voltage-setting mechanism – Distribution profile learned through simulation or dynamic learning Simple and energy-efficient detection is crucial Since errors are rare, its overhead is only of secondary importance § Error Detection – § Error Correction – Concept can be employed at many layers of the abstraction chain (circuit, architecture, system) VD D VDD setting Error Count Module Correction Low Power Design Essentials ErrorDetection 10. Error Rate versus Supply Voltage Example: 18x18 bit Multiplier @ 90 MHz on FPGA (using random input patterns) 35% energy savings with 1.3% error 22% saving Low Power Design Essentials [Courtesy: T. Austin, U. 10. Error Rate versus Supply Voltage Example: Kogge-Stone adder (870 MHz) (SPICE Simulations) with realistic input patterns 200 mV Low Power Design Essentials [Courtesy: T. Austin, U. 10. AD@Circuit Level ─ Razor Logic Main FF Main FF ME M Shadow Latch clk_d el clk clk_del cl k cl k § Error Detection – – Double-sampling latches (latch + shadow latch) detect timing errors Second sample is correct-by-design Microarchitectural support restores state Timing errors treated like branch miss-predictions § Error Correction – – § Challenges: metastability and short-path constraints Low Power Design Essentials [Ref: D. Ernst, Micro’03] 10. Razor: Distributed Pipeline Recovery IF PC Razor FF err or ID Razor FF err bubbl e or EX bubbl e Razor FF err or (readRazor FF only) bubbl err e or recov er flushID ME M (reg/m em) WB Stabilizer FF bubbl e recov er recov er flushID recov er flushID Flus h Con trol © IEEE 2003 flushID 3.3mm § § § IF ID EX WB Dcache Low Power Design Essentials [Ref: D. Ernst, Micro’03] 3.0mm 10. Builds on existing branch prediction framework Multiple cycle penalty for timing failure Scalable design as all communication is local Icache RF MEM Razor: Voltage Setting Mechanism Ediff = Eref Esample Er ef Edi ff Voltag e Contro l Functi on Voltage VD Regula D tor reset Pipeline . . . J Esam ple § Energy reduction can be realized with a simple proportional control function – Control algorithm implemented in software error signals Low Power Design Essentials [Ref: D. Ernst, Micro’03] 10. Energy/Performance Characteristics Pipeline Throughput Energy IPC Total Energy, Etotal = Eproc + Erecovery © IEEE 2003 Energy of Processor Operations, Eproc Energy of Processor w/o Razor Support Optimal Etotal Energy of Pipeline Recovery, Erecovery Decreasing Sup...
View Full Document

This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

Ask a homework question - tutors are online