Unformatted text preview: d) Parallel processors with own DC-DC converters Embedded in interposer Pads & bumps Package Stacked memories (thinned) Base chip Low Power Design Essentials [Ref: K. Onizuka, JSSC’07] 10. Summary
§ § § § § Power and energy optimality a function of operational parameters Run-time power optimization tracks changes in activity and environmental conditions to dynamically set supply and threshold voltages Aggressive deployment scales supply voltage below the traditional worst-case and uses error-detection/correction to deal with rare errors. Interesting idea: errors are not always fatal and can be allowed under certain conditions Challenge: Integrated power management and distribution supporting dynamic variations Low Power Design Essentials 10. Literature
Books, Magazines, Theses
§ T. Burd, Energy-Efficient Processor System Design,” http://bwrc.eecs.berkeley.edu/Publications/2001/THESES/energ_eff_process-sys_des/index.htm, UCB, 2001. Numerous authors, Better than worst case design, IEEE Computer Magazine, March 2004. T. Simunic: "Dynamic Management of Power Consumption", in Power-Aware Computing, edited by R. Graybill, R. Melhem, Kluwer Academic Publishers, 2002. A. Wang, Adaptive Techniques for Dynamic Processor Optimization, Springer, 2008. § § § Articles
§ L. Anghel and M. Nicolaidis, “Cost reduction and evaluation of temporary faults detecting technique,” Proc. DATE 2000, pp. 591–598, 2000. T. Burd,T. Pering, A. Stratakos, R. Brodersen; A dynamic voltage scaled microprocessor system, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1571 - 1580, November 2000. T. Chen and S. Naffziger, “Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation,” Trans. VLSI Systems, Vol 11, Isuse 5, pp. 888-899, Oct 2003. D. Ernst et al, “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation,” Micro Conference, December 2003. V. Gutnik,, A. P. Chandrakasan, "An Efficient Controller for Variable Supply Voltage Low Power Processing," IEEE Symposium on VLSI Circuits, pp. 158-159, June 1996. T. Kehl, “Hardware self-tuning and circuit performance monitoring,”: Proceedings ICCD 1993. T. Kobayashi, T. Sakurai; Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed 10. § § § § § § Low Power Design Essentials References (cntd)
§ T. Kuroda et al., “Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design”, IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 454-462, Mar. 1998. W. Liao, J. M. Basile, and L. He, “Leakage power modeling and reduction with data retention," in Proceedings IEEE ICCAD, pp. 714-19, San Jose, Nov. 2002. M. Miyazaki, J. Kao, A. Chandrakasan, "A 175mV Multiply-Accumulate Unit Using an Adaptive Supply Voltage Voltage and Body Bias (ASB) Architecture," IEEE ISSCC, pp. 58-59, San Francisco, California, February 2002. L. Nielsen, C. Niessen; Low-power operation using self-timed circuits and adaptive scaling of the supply voltage, IEEE Transactio...
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.
- Spring '10