Table lookup frequency voltage translation user logic

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Unformatted text preview: r Low Power Design Essentials 10. Table-Lookup Frequency-Voltage Translation User Logic Temp sensor VD D Ref Clk Calibration Unit (Delay analysis) Frequency-toVoltage Translation Table (F-V Table) Contr ol DCDC Conve rter Voltage-Frequency (V-F) relationship measured at start-up time (or periodically) Delay measurements for different voltages obtained from actual module or using array of ring oscillators § Inverse function (F-V) stored in look-up table, taking into account logic structure § Can compensate for temperature variations § Low Power Design Essentials [Ref: H. Okano, VLSI’06] 10. Example 2: General-Purpose Processor Applications supply completion deadlines. • Voltage Scheduler (VS) predicts workload to estimate CPU cycles. • Controller CPU cycles = Fdesired ∆time Required speed Clock & VDD FDESIRED (MHz) 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Processor Speed (MPEG) Software/ OS Hardware G.P. Processor Time (sec) Low Power Design Essentials 10. Impact of Voltage/Frequency Scheduling Normalized Energy Scheduling Algorithm ASAP Oracle Zero § Benchmarks MPEG 100% 67% 89% UI 100% 25% 30% Audio 100% 16% 22% Oracle: perfect knowledge of the future § Zero: heuristic scheduling algorithm § Largest savings when for less-demanding or bursty apps (UI, audio) § Difficult to get large gains in compute-intensive code (MPEG) Low Power Design Essentials [Ref: T. Pering, 10. Impact of Voltage Scheduling Example: User interface processing (very bursty) Compute ASAP: 3.5 Max. Speed 3.5 Increased speed for shorter process deadlines With Voltage Scheduler: VD D Idle 1.0 200ms/div VD D Low Speed & Idle 1.0 200ms/div High-latency computation done @ low speed/energy Low Power Design Essentials [Ref: T. Burd, 10. Converter Loop Sets VDD, fCLK Count er Latc h FME 7 AS fCL K Ring Oscillator PEN AB NEN AB Digital Loop Filter VB T RS T ID D Process or A f1M Hz 01101 00 Set by O.S. FD ES + Σ FE RR VDD L Regist er • Operating system set FDES • Ring oscillator delay-matched to CPU critical paths. • Feedback loop sets VDD so that FERR 0. Buck converter CD D Low Power Design Essentials [Ref: T. Burd, 10. A High-Performance Processor at Low-Energy 10 0 8 0 Dhrystone 2.1 MIPS 6 0 4 0 2 0 0 0 Dynamic VDD 6 MIPS @ 0.54 mW/ MIPS (1.2V) 2 85 MIPS @ 5.6 mW/MIPS (3.8V) Static VDD x 3 4 5 6 1 Energy (mW/MIPS) If processor in low-performance mode most of the time: 85 MIPS processor @ 0.54 mW/MIPS Low Power Design Essentials [Ref: T. Burd, JSSC’00] 10. Examples of DVS-Enabled Microprocessors § Early Research Prototypes – – Toshiba MIPS 3900: 1.3-1.9V, 10-40 MHz [Kuroda98] Berkeley ARM8: 1.2-3.8V, 6-85 MIPS, 0.54-5.6 mW/MIPS [Burd00] 0.7-1.75V, 200-1000MHz, 55-1500mW (typ) Max. Energy Efficiency: ~23 MIPS/mW 0.9-1.95V, 11-380MHz, 53-500mW (typ) Max. Energy Efficiency : ~11 MIPS/mW 0.8-1.3V, 300-1000MHz, 0.85-7.5W (peak) 0.95-1.5V, 600-1600MHz, 4.2-31W (peak) § Xscale: 180nm 1.8V bulk-CMOS – – § PowerPC: 180nm 1.8V bulk-CMOS – – § Crusoe:...
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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