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Unformatted text preview: ns on VLSI Systems, pp 391-397, December 1994. H. Okano, T. Shiota, Y. Kawabe, W. Shibamoto, T. Hashimoto, and A. Inoue, "Supply voltage adjustment technique for low power consumption and its application to SOCs with multiple threshold voltage CMOS," Symp. VLSI Circuits Dig. , pp. 208 - 209, June 2006. K. Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, “Stacked-chip Implementation of OnChip Buck Converter for Power-Aware Distributed Power Supply Systems,” A-SSCC, Nov. 2006. K. Onizuka, K. Inagaki, H. Kawaguchi, M. Takamiya, and T. Sakurai,IEEE JSSC, accepted, to be published, 2007. T. Pering, T. Burd, and R. Brodersen. “The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms.” Proceedings of Int’l Symposium on Low Power Electronics and Design 1998, pp.76-81, June 1998. H. Qin, Huifang Qin; Yu Cao; Markovic, D.; Vladimirescu, A.; Rabaey, J., "SRAM leakage suppression by minimizing standby supply voltage," Proceedings. 5th International Symposium on Quality Electronic Design, 2004, April 2004. J. Rabaey, “Power Management in Wireless SoCs,” Invited presentation MPSOC 2004, Aix-enProvence, Sept. 20004; http://www.eecs.berkeley.edu/~jan/Presentations/MPSOC04.pdf 10. § § § § § § § § § Low Power Design Essentials References (cntd)
§ T. Sakurai; Perspectives on power-aware electronics, IEEE International Solid-State Circuits Conference, vol. XLVI, pp. 26 - 29, February 2003. M. Seeman, S. Sanders, J. Rabaey, “An Ultra-Low-Power Power Management IC for Wireless Sensor Nodes”, Proceedings CICC 2007, San Jose, Sept. 2007. A. Sinha, A. P. Chandrakasan, "Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces," VLSI Design 2001, pp. 221-226, Bangalore, India, January 2001. M. Sheets et al, "A Power-Managed Protocol Processor for Wireless Sensor Networks," Digest of Technical Papers VLSI06, pp. 212 – 213, June 2006. B. Shim and N. R. Shanbhag, “Energy-efficient soft error-tolerant digital signal processing,” IEEE Transactions on VLSI, 14, 4, 336-348, April, 2006 J. Tschanz et al.; Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage, IEEE International Solid-State Circuits Conference, vol. XLV, pp. 422 - 423, February 2002. A. Uht, “Achieving typical delays in synchronous systems via timing error toleration,” Technical Report TR-032000-0100, University of Rhode Island, Mar. 2000. G. Varatkar, N. Shanbhag, “Energy-Efficient Motion Estimation using Error-Tolerance,” Proceedings ISLPED 06, pp. 113-118, Oct 2006. F. Worm, P. Ienne, P. Thiran, and G. D. Micheli. “An adaptive low-power transmission scheme for on-chip networks,” Proc. of the International Symposium on System Synthesis (ISSS), pages 92– 100, 2002. § § § § § § § § Low Power Design Essentials 10....
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