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Clock-Gating and Its Application to Low Power Design
of Sequential Circuits
Qing Wu, Massoud Pedram, and Xunwei Wu
This paper models the clock behavior in a sequential circuit
by a quaternary variable and uses this representation to propose and an-
alyze two clock-gating techniques. It then uses the covering relationship
between the triggering transition of the clock and the active cycles of var-
ious flip flops to generate a derived clock for each flip flop in the circuit. A
technique for clock gating is also presented, which generates a derived clock
synchronous with the master clock. Design examples using gated clocks are
provided next. Experimental results show that these designs have ideal logic
functionality with lower power dissipation compared to traditional designs.
Clock gating, CMOS, logic, low power, sequential circuit,
The sequential circuits in a system are considered major contributors
to the power dissipation since one input of sequential circuits is the
clock, which is the only signal that switches all the time. In addition,
the clock signal tends to be highly loaded. To distribute the clock and
control the clock skew, one needs to construct a clock network (often
a clock tree) with clock buffers. All of this adds to the capacitance of
the clock net. Recent studies indicate that the clock signals in digital
computers consume a large (15–45%) percentage of the system power
. Thus, the circuit power can be greatly reduced by reducing the
clock power dissipation.