clockgate

clockgate - 415 IEEE TRANSACTIONS ON CIRCUITS AND...

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415 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO. 103, MARCH 2000 [13] E. Ott, C. Grebogi, and J. A. Yorke, “Controlling chaos,” Phys. Rev. Lett. , vol. 64, pp. 1196–1199, 1990. [14] F. R. Marotto, “Snap-back repellers imply chaos in ` ,” J. Math. Anal. Appl. , vol. 63, pp. 199–223, 1978. [15] T. Y. Li and J. A. Yorke, “Period three implies chaos,” Amer. Math. Monthly , vol. 82, pp. 481–485, 1975. [16] G. H. Golub and C. F. Van Loan, Matrix Computations . Baltimore, MD: Johns Hopkins Univ. Press, 1983. [17] K. Shiraiwa and M. Kurata, “A generalization of a theorem of Marotto,” in Proc. Japan Acad. , vol. 55, 1980, pp. 286–289. [18] T. Ushio and K. Hirai, “Chaos in nonlinear sampled-data control sys- tems,” Int. J. Contr. , vol. 38, pp. 1023–1033, 1983. [19] T. Ushio and K. Hirai, “Chaotic behavior in piecewise-linear sam- pled-data control systems,” Int. J. Nonlinear Mech. , vol. 20, pp. 493–506, 1985. [20] L. Chen and K. Aihara, “Chaos and asymptotical stability in dis- crete-time neural networks,” Physica D , vol. 104, pp. 286–325, 1997. [21] G. Chen, S.-B. Hsu, and J. Zhou, “Snapback repellers as a cause of chaotic vibration of the wave equation with a van der Pol boundary con- dition and energy injection at the middle of the span,” J. Math. Phys. , vol. 39, pp. 6459–6489, 1998. [22] E. Bollt, “Stability of order: An example of chaos “near” a linear map,” Int. J. Bifurcat. Chaos , vol. 9, no. 10, pp. 2081–2090, 1999. Clock-Gating and Its Application to Low Power Design of Sequential Circuits Qing Wu, Massoud Pedram, and Xunwei Wu Abstract— This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and an- alyze two clock-gating techniques. It then uses the covering relationship between the triggering transition of the clock and the active cycles of var- ious flip flops to generate a derived clock for each flip flop in the circuit. A technique for clock gating is also presented, which generates a derived clock synchronous with the master clock. Design examples using gated clocks are provided next. Experimental results show that these designs have ideal logic functionality with lower power dissipation compared to traditional designs. Index Terms— Clock gating, CMOS, logic, low power, sequential circuit, synthesis. I. INTRODUCTION The sequential circuits in a system are considered major contributors to the power dissipation since one input of sequential circuits is the clock, which is the only signal that switches all the time. In addition, the clock signal tends to be highly loaded. To distribute the clock and control the clock skew, one needs to construct a clock network (often a clock tree) with clock buffers. All of this adds to the capacitance of the clock net. Recent studies indicate that the clock signals in digital computers consume a large (15–45%) percentage of the system power [1]. Thus, the circuit power can be greatly reduced by reducing the clock power dissipation.
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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clockgate - 415 IEEE TRANSACTIONS ON CIRCUITS AND...

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