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Unformatted text preview: Energy Energy Efficient Circuit Design and the Future of Power Delivery Greg Taylor EPEPS 2009 Outline Outline • Looking back • Energy efficiency in CMOS • Side effects • Suggestions • Conclusion Energy Efficient Circuit Design and the Future of Power Delivery 2 Looking Looking Back • Microprocessor scaling has been a topic of interest both at EPEP and to the IC design community in general – MOS scaling helps set our expectations for scaling helps the the future – Microprocessors tend to bound the high power density edge of the product space Energy Efficient Circuit Design and the Future of Power Delivery 3 EPEP EPEP 2003 • In his “Architecting Interconnect” address, Peter Hofstee identified the major challenges facing microprocessors: – – – – Software inertia I/O bandwidth Power delivery Cooling • The future is simpler architecture and more cores Energy Efficient Circuit Design and the Future of Power Delivery 4 SPI SPI 2004 • In my “Design Challenges of the 90 nm Pentium® 4 Processor” address highlighted similar issues: – – – – Power delivery Cooling Variation Gate leakage • But scaling will continue Energy Efficient Circuit Design and the Future of Power Delivery 5 Power Power density vs CD 1000 Rocket Nozzle Nuclear Reactor 100 W/cm2 Pentium® II processor 10 Pentium® 4 processor Core 2 Duo® processor Pentium® III processor Hot Plate Pentium® Pro processor Atom™ Processor Pentium® processor i486 i386 1 10 1 0.1 0.01 CD (µm) Energy Efficient Circuit Design and the Future of Power Delivery 6 Energy Energy Efficiency in CMOS • CMOS power is determined by C, V, f: – Power ~ CV2f + IleakV • Process technology can improve C • Reducing V reduces performance reduces • Delay ~ C * Vcc/(Vcc – Vt)α Vcc/(Vcc • But it reduces power even faster – Ileak is also a function of V Energy Efficient Circuit Design and the Future of Power Delivery 7 Frequency Frequency and Power Measurements Maximum Frequency (MHz) 104 103 102 101 1 0.2 101 1 10 10-1 10-2 1.4 Total Power (mW) 8 65nm CMOS, 50°C 102 0.4 0.6 0.8 1.0 1.2 Supply Voltage (V) • From: A 320mV 56µW 411GOPS/Watt UltraUltra-Low Voltage Motion Estimation Accelerator in 65nm CMOS – ISSCC ‘08 EnergyEnergy-Efficiency Measurements 375 300 225 150 75 0 0.2 0.4 0.6 0.8 1.0 Supply Voltage (V) 1.2 320mV 9.6X 10-1 10-2 1.4 1 Active Leakage Power (mW) (mW) 9 450 Energy Energy Efficiency (GOPS/Watt) (GOPS/Watt) 65nm CMOS, 50°C 101 • From: A 320mV 56µW 411GOPS/Watt UltraUltra-Low Voltage Motion Estimation Accelerator in 65nm CMOS – ISSCC ‘08 10 Voltage Voltage Scaling Voltage (V) 5 4 3 2 0.7x/gen 1 2000 1000 800 500 350 250 180 130 90 65 45 CD (nm) • Voltage scaling has slowed on recent technologies – This is the technology maximum voltage Energy Efficient Circuit Design and the Future of Power Delivery 10 Side Side Effects • Reduced voltage operation increases sensitivity to temperature and within die variation – RDF sensitivity of state elements is increased increased requiring redesign or larger sizes – SRAM Vmin tends to increase on more aggressive technologies – Combinatorial delay variation is increased Energy Efficient Circuit Design and the Future of Power Delivery 11 Temperature Temperature Induced Variations 104 Maximum Frequency (MHz) (MHz) 103 110°C 102 50°C 0°C 101 1 0.2 ±2X 65nm CMOS Typical Die Measurements ±5% Frequency variation across across 0-110°C 320mV 0.4 0.6 0.8 1.0 Supply Supply Voltage (V) 1.2 1.4 • Frequency variation across 0-110°C: 0– Increases from ±5% at 1.2V to ±2X at 320mV Energy Efficient Circuit Design and the Future of Power Delivery 12 Low Low Voltage Process Variations Normalized Distribution 1 65nm CMOS Monte Carlo Simulations, 50°C 1.2V ±18% ±2X 320mV 0 0.5 Frequency variation across fast-slow skews fast- 1.0 1.5 Normalized Frequency 2.0 ● Frequency variation across fast-slow skews: fastskews: ● Increases from ±18% at 1.2V to ±2X at 320mV Energy Efficient Circuit Design and the Future of Power Delivery 13 Supply Supply Voltage Compensation Frequency (MHz) 42 28 23MHz 14 0 0 50 110 Temperature (°C) Frequency (MHz) 56 65nm CMOS, 320mV Typical Die 56 42 28 14 0 Slow Typical Fast Process Skew 23MHz 65nm CMOS, 320mV, 50°C • Adjust supply voltage to maintain constant performance • ±50mV adjustment about 320mV: Nominal Nominal 23MHz performance sustained across 0-110°C 0and fast-slow skews fastEnergy Efficient Circuit Design and the Future of Power Delivery 14 Other Other Side Effects • Very low power delivery impedance • Granularity: Each core may differ • Stability of state elements: Vmin – Some invention needed • Test – Adaptation to performance, Vmin – Slowest low voltage operation is at cold – Do we need to operate across the supply range? Energy Efficient Circuit Design and the Future of Power Delivery 15 Suggestions Suggestions • Take advantage of many cores • Use fine grained power management to overcome within die variations • On die/pkg, point of load regulation • Adaptation is a test challenge Power VR VR VR VR VR VR Core Core Core Core Core Core I/O Energy Efficient Circuit Design and the Future of Power Delivery 16 How How Will This Change Power Delivery? • Regulator inefficiency moves on die + Under the big heat sink – But the hot spot gets hotter + Reducing voltage wherever possible reduces reduces overall power Energy Efficient Circuit Design and the Future of Power Delivery 17 How How Will This Change Power Delivery? • Eliminate multiple regulators from the motherboard + Fewer components + Higher voltage, lower current requirements Energy Efficient Circuit Design and the Future of Power Delivery 18 How How Will This Change Power Delivery? • Regulators are constant power loads – Which means negative input impedance + Power supply and package designers still have have interesting work to do Energy Efficient Circuit Design and the Future of Power Delivery 19 How How Will This Change Power Delivery? • Regulators will be needed inside the die/package – Need to deal with “high” voltages and precision precision analog electronics on microprocessors microprocessors + New power management opportunities will arise Energy Efficient Circuit Design and the Future of Power Delivery 20 Conclusion Conclusion • Power delivery, cooling, and variation are still challenges for many core chips • Power efficient performance has become become a key processor metric • Operation at very low supply voltage offers significant improvement in power efficiency • These combine well with the previously identified many core direction Energy Efficient Circuit Design and the Future of Power Delivery 21 Conclusion Conclusion (cont) • Low voltage operation significantly exacerbates within die variation • Distributed, on die supply regulation can can compensate for this variation – Bringing new design, manufacturing, and test challenges Energy Efficient Circuit Design and the Future of Power Delivery 22 Thank Thank You Energy Efficient Circuit Design and the Future of Power Delivery ...
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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