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# Ex212 - ECE260B/CSE241A Exercise Exercise 1 Scaling Trend...

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ECE260B/CSE241A Exercise February 12, 2010 Exercise 1. Scaling Trend: Describe the scaling trend of delay, power, and energy per instruction according to the following model. Depict your assumptions. 1) Conventional long channel model. 2) Short channel model. 3) ITRS roadmap. Exercise 2. Logic Effort Calculation. In order to implement OR4 logic in 45nm process to drive a 10fF on-chip capacitance, we end up with two options, (A) NOR4+INV; (B) 2 NOR2 + NAND2, as shown below. Assuming sizes of all the logic gates are tuned to follow the inverter with 2:1 P/N ratio and per unit width gate capacitance C perwidth =1.5fF/um. 1) Calculate the size ratio of NAND2 in option (B) to make (A) and (B) achieve the same delay. (neglect all the parasitic capacitance during calculation and the minimum CMOS transistor width W min =2L, where L is the feature size.) 2) Which option saves more dynamic power, and why? Exercise 3. Flip-Flop Analysis. For the conventional master-slave D flip-flop design shown below, 1) Explain the basic working principle of this flip-flop.

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