FinProj - ECE260B/CSE241A Final Project Designing Low Power...

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1 ECE260B/CSE241A – Final Project Designing Low Power 16-bit Adder Due Date: Midnight 03/19 Objective: Understand the principles of designing low power function blocks. Applying low power techniques to design a function block. Note: All of the following assignments are based on the PTM (predictive technology model) 32nm technology provided by Arizona State University, available at: http://ptm.asu.edu/. Needed SPICE model files, interface and input vectors will be provided. All the simulations are performed in HSpice ® . Project: Designing Low Power 16-bit Adder Module The goal of the project is to design a low power 16-bit adder. You can apply any low power design techniques of your choice to design the 16-bit adder. The goal of the project is to minimize “ Total energy × Total delay × Total area ” in your adder design which is your design metric. You will compete with other groups to minimize your design metric. Group with the minimum metric will get the full credit and the rest of the groups are ranked accordingly. The design should use 32nm process. Use provided input test vector patterns to verify your design. 16-bit adder A[15. .0] B[15. .0] S [15. .0] C in C out V dd V ss Adder Design) Design your 16-bit adder. You can design your adder with any low power design technique of your choice. You can design an either synchronous or asynchronous adder. The objective of
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FinProj - ECE260B/CSE241A Final Project Designing Low Power...

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