Ishihara_ISLPED03

Ishihara_ISLPED03 - Level Conversion for Dual-Supply...

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Level Conversion for Dual-Supply Systems Fuji0 Ish i ha ra' ,* Farhana Sheikh' Borivoje Nikolic' 'Department of EECS, University of California, Berkeley, USA Broadband System LSI Project, System LSI Division, Toshiba Corporation, Japan {fuji, farhana, bora}@eecs.berkeley.edu 2 ABSTRACT Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. Novel flip-flops presented in this paper incorporate a half-latch LC and a precharged LC. These flip-flops are optimized in the energy-delay design space to achieve over 30% reduction of energy-delay product and about 10% savings of total power in a CVS design as compared to the conventional flip- flop. These benefits are accompanied by 24% robustness improvement and 18% layout area reduction. Categories and Subject Descriptors General Terms Keywords B.6.1 [Design Styles]: Sequential circuits - design styles. Design, Performance. Level conversion, dual-supply voltage, flip-flop. 1. INTRODUCTION Power dissipation is a limiting factor in both high-performance and mobile applications. Independent of application, desired performance is achieved by maximizing operating frequency under power constraints that may be dictated by battery life, chip packaging andor cooling costs. Lowering supply voltage results in a quadratic reduction in power dissipation but significantly impacts delay. In constant-throughput applications, this performance loss is recovered by increased pipelining or parallelism [ 11, but it increases the latency of the design. A multiple supply voltage design in which a reduction in supply voltage is applied only to circuits outside critical paths can save power without sacrificing either throughput or latency. A key challenge in designing efficient multiple-supply circuits involves minimizing the cost of level converters (LC) placed on the boundary between 1ow-V~~ (VDDL) and high-VDD (VDDH). A level converter restores a VDDH swing from a VDDL signal in order to prevent DC current due to incomplete PMOS cut-off. A PMOS cross-coupled LC [ 121 is widely used to suppress the DC current. While cost-minimized level conversion has been proposed for a custom data-path design [SI, an effective solution for synthesized Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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Ishihara_ISLPED03 - Level Conversion for Dual-Supply...

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