ISSCC_09_Itoh

ISSCC_09_Itoh - ISSCC2009 Keynote Adaptive Circuits for the...

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Adaptive Circuits for the 0.5-V Nanoscale CMOS Era Kiyoo Itoh Hitachi Ltd., Tokyo, Japan ISSCC2009 Keynote © 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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K. Itoh OUTLINE 1. Introduction The 1-V wall 2. Adaptive Circuits for Memory-Rich LSIs Trends in V min Breakthrough technologies Scenario to the 0.5-V nanoscale era 3. Adaptive Circuits for Mixed Signal LSIs Digital assisted analog design 4. Conclusion © 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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K. Itoh The 1-V Wall Device feature size, F (nm) 800 350 90 45 22 11 V DD Target 180 min (RDF) 5 4 3 2 1 0.4 DD , V (V) 0.2 0.6 0.8 MPUs(ISSCC), : Min. op. Power crisis RDF: Random Dopant Fluctuation © 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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K. Itoh What should we do to lower V DD ? 1. Reduce min. operating V (V min ) by reducing •Lowest necessary V t (V t0 ), •Intrinsic V -variation ( Δ V ). New devices, circuits, repair etc. 2. Reduce power-supply noise (V ps ) Compact subsystems (small core/chip, 3-D chip stack) etc. Reducing V is the key. (V »V ) © 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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K. Itoh OUTLINE 1. Introduction The 1-V wall 2. Adaptive Circuits for Memory-Rich LSIs Trends in V min Breakthrough technologies Scenario to the 0.5-V nanoscale era 3. Adaptive Circuits for Mixed Signal LSIs Digital assisted analog design 4. Conclusion © 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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K. Itoh Circuits Giving Low-V DD Limitations * Most sensitive to Δ V t large largest small LW 8F 2 (av.) 1.5-3F 2 15F 2 Count large largest medium Inverter SRAM Cell * DRAM SA * 1/ LW, F : device feature size Chip Logic block RAM block Peri. Array DL cell WL DL © 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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K. Itoh Definition of V min τ (V t ) V DD /(V DD –V ) 1.2 Δτ = (V t0 + Δ tmax )/ (V ) ={(V –V )/(V –V t0 )} 1.2 : Lowest necessary av.V Tmax :Max. ±variation ±in±V =V for a fixed =V + (1 + γ ) = 1/( 1/1.2 –1) : Tolerable speed variation γ≅ 2–3 for =1.4 –1.6 Inverter SRAM Cell DRAM SA DL DL 0 SP - v S DL SN DL © 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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K. Itoh High and Unscalable V t0 Subthreshold leakage (A) 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 -0.2 0 0.2 0.4 0.6 1 T j = 75 ° C, 130 nm V t0 (ext, 25 ° C) (ext) = (nA/ μ m) + 0.3 V 1-Mgate Logic 1-Mb SRAM 64-K DRAM SAs* 0.8 HP LP HP LP * contributing to leakage in active standby mode HP: high performance, LP: low power © 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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K. Itoh Δ V tmax K. Itoh et al., p. 68, ESSCIRC2007 K. Takeuchi et al., p. 467, IEDM 2007 = m σ •m circuit count = A vt / LW {t ox (V t0 + 0.1 V)} 0.5 N sub 0.25 For lower , use 1. Repair ECC + Redundancy (m ->1/2) 2. Small technologies •Circuits tolerating The largest MOSFET possible The lowest V t0 possible •Small-A MOSFETs A (mV μ m), t OX (nm) Device feature size, F (nm) 10 5 4 3 2 1 0.5 0.4 0.3 2.5 1.5 FD-SOI, EOT = 0.5 nm 250 130 90 65 45 32 180 4.2 Conv. ( ) High-k MG ( ) FD-SOI ( ) © 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE
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K. Itoh ECC + Redundancy Redundant Words •ECC word with one defect cell corrected by ECC.
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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ISSCC_09_Itoh - ISSCC2009 Keynote Adaptive Circuits for the...

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