Itoh_ISSCC09

Itoh_ISSCC09 - 14 2009 IEEE International Solid-State...

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Unformatted text preview: 14 2009 IEEE International Solid-State Circuits Conference ISSCC 2009 / SESSION 1 / PLENARY / 1.2 1.2 Adaptive Circuits for the 0.5-V Nanoscale CMOS Era Kiyoo Itoh Fellow, Hitachi, Tokyo, Japan 1. Introduction Low-voltage scaling limitations of memory-rich CMOS LSIs are one of the major problems in the nanoscale era [1-3] because they cause the ever- more-serious power crises with device scaling. The problems stem from two unscalable device parameters: The first is the high value of the lowest necessary threshold voltage, V t (that is, V t0 ), of MOSFETs needed to keep the subthreshold leakage low. Although many intensive attempts to reduce V t0 through reducing leakage have been made since the late 1980s [3-5], V t0 is still not low enough to reduce the operating voltage, V DD , to the sub-1V region. The second is the variation in V t (that is, V t ), that becomes more prominent in the nanoscale era [1-3]. The V t caused by the intrinsic ran- dom dopant fluctuation (RDF) is the major source of various V t compo- nents. It increases with device scaling and thus enhances various detrimen- tal effects such as variations in delay (and speed) and/or the voltage mar- gins of circuits, and it significantly increases soft-error rates in RAM cells and logic gates. To offset such effects, V DD must be increased with device scaling, which causes an increase in the power dissipation, as well as degrades the device reliability due to increased stress voltage. Due to such inherent features of V t0 and V t , V DD is facing the 1V wall in the 45nm gen- eration, and is expected to rapidly increase with further scaling of poly-Si bulk MOSFETs [1-3], as shown in Figure 1.2.1. To reduce V DD , the minimum usable power supply V DD (that is, V min ) determined by the above-described V t0 and V t must be reduced, while the power-supply integrity is ensured. This is because V DD is the sum of V min , the power-supply droop and noise in power supply lines/substrate, (that is, V ps ), and V , where V ps is usually much higher than V in the nanoscale era. Here, V is the sum of the nec- essary voltages for compensating for the extrinsic V t due to short-channel effects and line-edge roughness, and for meeting the speed target. Thus, V depends on the qualities and maturity of the fabrication process and the design target, which cannot be specified here. An associated problem in the nanoscale era is the ever-higher resistance of interconnects [6-8]. This is also closely related to the voltage-limitation problem at the chip and subsys- tem levels, since it degrades not only the speed of ever-larger chips, but also effects power-supply integrity by increasing V ps . As well, integrity depends on chip packaging such as 3D integration [9]....
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Itoh_ISSCC09 - 14 2009 IEEE International Solid-State...

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