LAB1 - ECE260B/CSE241A - Project 1 Power Analysis of...

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ECE260B/CSE241A - Project 1 Power Analysis of Combinational Logic Gates Lab Posted: 1/8 (Friday) Due Date: 1/26 (Tuesday) Objective: obtain an overview on how the power (dynamic and leakage) is consumed in transistors and simple logic gates, also get familiar with the energy-delay trade-off in the low-power design. Note: All the following assignments are based on the PTM (predictive technology model) provided by Arizona State University, available at: http://ptm.asu.edu/. Needed SPICE model files and some sample netlists will be provided. All the simulations are performed in HSpice ® . Lab Assignments: Part 1: Study the I on and I off of a single transistor For a min-sized single CMOS transistor w/ 4 terminals (Gate, Drain, Source, and Body) controlled by voltage sources, perform the following steps: Step 1) Show the I-V characteristic of a 65nm PMOS and NMOS transistor where V DS ranges from 0 to 1.1V incrementing by 0.1V for five V GS values increment by 0.2V between 0.1V and 1.1V. Draw the I-V curve. Step 2) Show all the leakage effects of a 65nm CMOS transistor (PMOS and NMOS) where V GS varies from -0.5 to 1.1V incrementing by 0.1V for three V DS
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LAB1 - ECE260B/CSE241A - Project 1 Power Analysis of...

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