LAB1_example

LAB1_example - 1/19/2010 2 Part1 I-V characteristic of MOS...

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ECE260B/CSE241A Project 1 - Power Analysis of Combinational Logic Gates Yulei Zhang 2010/01/19
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Agenda of Project 1 Part 1: Study I ON and I OFF (leakage) of single transistor. I-V characteristic of transistors. Study of leakage current. Impact of technology scaling (65nm~32nm) on I ON /I OFF. Side effects: temperature, body biasing. Part 2: Study E-D trade-off of a loaded inverter. Plot E-D trade-off curves for different inverter sizes/different voltages. Discuss how to choose the best size/V DD for given delay constraint. Part 3: Detailed power analysis of combinational logic gates. Design gate size to achieve similar performance. (logical efforts) Show how to choose the better logic option in terms of energy. Measure static/dynamic power dissipation for different technologies.
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Unformatted text preview: 1/19/2010 2 Part1 I-V characteristic of MOS transistors 65nm min-size NMOS V GS =1.1V V GS =0.9V V GS =0.7V V GS =0.5V V GS =0.3V V GS =0.1V 1/19/2010 3 Part 1 Study of all leakage effects 65nm min-size NMOS V DS =1.1V V DS =0.5V V DS =0.1V 1/19/2010 4 Part1 Study of temperature effects 65nm min-size NMOS 1/19/2010 5 Part1 Study of body biasing 65nm min-size NMOS 1/19/2010 6 Part2 Energy-Delay Tradeoff Study 1/19/2010 7 Inverter driving 100fF cap. Sweep V DD w/ fixed size Sweep size w/ fixed V DD Size: 10X Size: 50X Size: 100X V DD =0.6V V DD =1.1V V DD =1.5V Part3 Power analysis of combinational logic gates 1/19/2010 8 E-D tradeoff of two structures to Implement AND4 logic @ 45nm...
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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LAB1_example - 1/19/2010 2 Part1 I-V characteristic of MOS...

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