LAB2 - ECE260B/CSE241A - Project 2 Power Analysis of...

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ECE260B/CSE241A - Project 2 Power Analysis of Flip-Flops and Memories Lab Posted: 1/26 (Tuesday) Due Date: 2/9 (Tuesday) Objective: Understand the basic principle of level shifters, and design state-of-the-art Level-Converting Flip-Flops at the transistor-level. Familiar with the Static Noise Margin (SNM) of SRAM cell, also understand the trade-off between SNM and supply voltage (energy) in the SRAM design. Note: All the following assignments are based on the PTM (predictive technology model) provided by Arizona State University, available at: http://ptm.asu.edu/. Needed SPICE model files and basic sample netlists will be provided. All the simulations are performed in HSpice ® . Lab Assignments: Part 1: Design of Level-Converting Flip-Flops (LCFFs) For a level-converting flip-flop shown below [Ishihara ISLPED’03], design the transistor size to achieve the right function (level-shifting and data latching). The design should use 45nm process. Low-V DD and high-V DD should be 0.8V and 1.1V , respectively. Assume there is a 100fF load capacitance at the output of flip-flop, and the slew of output signal is no larger than 100ps . Use SPICE transient simulation w/ provided input test patterns to verify your design. Step 1)
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LAB2 - ECE260B/CSE241A - Project 2 Power Analysis of...

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