LAB3 - ECE260B/CSE241A - Project 3 Power Analysis of...

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1 ECE260B/CSE241A - Project 3 Power Analysis of Function Blocks Due Date: 03/07 Objective: Understand the basic principle of power gating and its impact on logic. Familiarize yourself with runtime timing errors correction during low power operations. Note: All of the following assignments are based on the PTM (predictive technology model) provided by Arizona State University, available at: http://ptm.asu.edu/. Needed SPICE model files and basic sample netlists will be provided. All the simulations are performed in HSpice ® . Lab Assignments: Part 1: Impact of Power Gating on Low Power Operations Footer and header switches are used to reduce the leakage power during standby mode. For the given 4-bit adder you can use either header switch or footer switch based on the design objective. The design should use 45nm process. Note that the effective V dd and V ss of the logic is V dd1 and V ss1 . Use SPICE transient simulation w/ provided input test patterns to verify your design. 4-bit adder A[0. .3] B[0. .3] S [0. .3] C in C out V dd Footer Header V ss V ss1 V dd1 V DDmain R die C die Add in step 3 Step 1) The Objective in this step to maximize the I on /I off ratio for the path from V dd1 and V ss1 . We use 45nm process for this step. Based on the I on /I off choose the proper switch either header or footer and the proper transistor size to maximize the I
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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LAB3 - ECE260B/CSE241A - Project 3 Power Analysis of...

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