Ling_ISQED07

Ling_ISQED07 - Repeated On-Chip Interconnect Analysis and...

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Unformatted text preview: Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals Ling Zhang 1 , Hongyu Chen 2 , Bo Yao 3 , Kevin Hamilton 4 , Chung-Kuan Cheng 1 1 University of California, San Diego, CA 92093, 2 Synopsys Inc., CA 94043 3 Mentergraphics Corp., CA 95131, 4 Qualcomm Inc., CA 92121 1 { lizhang, ckcheng } @cs.ucsd.edu, 2 hongyu.chen@synopsys.com 3 bo yao@menter.com, 4 kevinham@qualcomm.com Abstract As semiconductor process technologies shrink, interconnect planning presents ever-greater challenges to designers. In this paper, we analyze, evaluate and compare various metrics with optimized wire configurations in the contexts of different de- sign criteria: delay minimization, delay-power minimization and delay 2-power minimization. We show how various design cri- teria influence interconnect performance and we have several observations: (1) the optimal inverter to wire capacitance ra- tio depends only on the technology and design goal, not on wire pitch, (2) at min-pitch, the width pitch ratios of wire for different objective functions are different: the ratio is 0.52 for minimiz- ing delay, 0.31 for minimizing delay 2-power product and 0.21 for minimizing delay-power product, (3) we derive the quantita- tive delay-energy trade-offs for the three objective functions: the delay-power product reduces power by 67% with a cost of 40% larger delay, while the delay 2-power product reduces power by 50% with a cost of 10% larger delay, which implies that delay 2- power product results a decent power saving with little cost on speed and (4) We derive the quantitative results of the impact of wire pitch on wire performance. Particularly at 70nm technology node, for bandwidth, the optimal pitch is at min-pitch, while for power, the optimal pitch is 2.35x the min-pitch, and for bandwidth over power, the optimal pitch is 1.76x min-pitch. 1. Introduction Interconnect strategy, or interconnect planning has become a critical part of chip design. One well-known reason for this comes from the growing significance of wire delay relative to gate delay in the total delay equation. [4] noted that RC de- lay is dominated by the global interconnect component and that the benefits of new materials alone are insufficient to meet over- all long-term performance requirements. Another important fac- tor is the increasing relative power consumption of wires versus gates. In [8], the authors found that interconnect power alone accounted for half the total dynamic power of a 0.13um micro- processor that was designed for power efficiency. As a result, interconnect power consumption has the potential to be a limit- ing factor in the realization of Moores law....
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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Ling_ISQED07 - Repeated On-Chip Interconnect Analysis and...

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