Matt - Low Power SOC Design and Automation Matt Severson...

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Matt Severson Qualcomm CDMA Technologies July 27, 2009 Low Power SOC Design and Automation
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Introduction Overview of Serra (Qualcomm’s first 45nm tapeout) Features / Technology / Low Power Techniques Tradeoffs of Automated vs. Custom Design for Low Power Memory IP Standard Cell Mixed-Vt Design Clock Power Clock Gating Clock Tree Synthesis Multiple Power Domains Voltage Scaling Voltage Islands with Power Gating Outline 2 July 2009
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Introduction Power consumption is a key differentiator in wireless communications products. Power Consumption Limits Battery Life Performance Feature set Form Factor 3 July 2009
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Introduction – Form Factor July 2009 4 Phone Surface Temperature Rise Above Ambient Surface Power Density [W/sq-in] 0.02 0.03 0.05 0.07 0.2 0.3 0.5 0.8 0.01 0.1 1 Temperature Rise, [C] 2 3 5 7 20 30 50 80 1 10 100 Surface Power Densities less than 0.1 W/sq-in This is the recommended design area Surface Power Densities between 0.1 and 0.22W/sq-in Phone is likely to have local hot spots Surface Power Densities greater than 0.22W/sq-in Phone should be redesigned Power Densities Increasing Overheating Limit Form Factors
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Introduction - Battery Life 5 July 2009 44% 43% 21% 28% 14% 26% 35% 12% 19% 48% 0% 20% 40% 60% 80% 100% Device 1 Device 2 Device 3 Device 4 Device 5 Device 6 Device 7 Device 8 Device 9 Device 10 % of Total Reviews Battery Life Analysis 1 Star (Bad) 2 Stars 3 Stars 4 Stars 5 Stars (Good) Expressed Dissatisfaction Verizon™ A Battery Capacity Screen Pixels 860 mAh 800 mAh 800 mAh 1400 mAh 240 x 320 240 x 320 240 x 320 360 x 480 930 mAh 1300 mAh 1130 mAh 1500 mAh 910 mAh 880 mAh 240 x 320 240 x 400 240 x 320 240 x 320 240 x 320 176 x 220 Phone Chipset
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SERRA Qualcomm’s First 45nm Tapeout July 2009 6
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Serra Feature Set July 2009 7 Modem o o UMTS (includes HSDPA, HSUPA) o GSM (includes GPRS and EDGE) o Unified GPS engine for both CDMA and UMTS modes. Processors o QDSP4u8 based MDSP core o ARM11 core with 32KB I/D cache o ARM926 core with 32KB I/D cache o QDSP5u4 based ADSP core w/ 256 KB L2 cache Multimedia o 24 bit WVGA w/ LCDC (active refresh) o ATI LT graphics core (Open GL 2.0) o 22M Triangles/Sec o 8 Mpixel Camera support Peripherals 2 HS USB interfaces o MDDI gen 1.5
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Serra Physical Characteristics Die size: 8200.08 x 6500.34 um (53.3 mm^2) Signal I/Os: 419 Process: tsmc45lp Metal Layers: 6 (5 thin, 1 thick (4x)) and 1 AP RDL layer Total # Transistors: 170 Million Total # RAM bits: 13.7 Mbits Total # ROM bits: 1.1 Mbits Static IR Drop: < 10mV (@ Worst case 800 mA) Leakage: ~450 uA (TT,25c, 1.125V) 671 pin 13x13 NSP Package 0.5mm ball pitch Includes Serra (Digital die) + Analog + Memory 8 July 2009
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Serra Low Power Design Goals Background Leakage Power is increasing due to process 45nm Sub-Threshold is worse than 65nm (pA/um) Gate leakage is increasing. Junction Diode leakage is increasing.
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Matt - Low Power SOC Design and Automation Matt Severson...

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