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Unformatted text preview: EAL! Cream, (20 mel +2: :0 ECE26OB/CSE241A Midterm, February 16, 2010, Name Sal “Ham 1. Scaling Trend: Describe the scaling of delay, power, energy per instruction and
power density according to the following models. Suppose that the technology
allows three dimensional ICs, i.e. 10 dies are stacked via through silicon vias.
Assume that the frequency and die size are ﬁxed, while the voltages V44, V”, drop, the
geometries of the transistor, W, L, T0,, shrink, and the number of IC dies increases with the same scaling. All scale with a factor S.
L 10 (As) 1) Long channel model (a = 2 in the alpha power law model). gmiﬂ‘lmskwr Mir”; Dgw¥rt£§ CW VM)N°‘ (yS)N ,2? 01:). 12961115“ CA’ W“‘ x—é— sham mnsiﬁw WWWWW‘ ‘3;
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PM A“? on mm . 5] U0 ([5) 2) Short'channel model (a = 1.2 in the alpha power law model).
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PW x m W7 /.hc,hu11‘w d m PM We °( LU 2. Dynamic Voltage Scaling: For dynamic voltage scaling, the supply voltage ﬂuc
tuates according to a controlled scheduling to balance between system performance
and power consumption. Describes the logic behavior of the following logic style
when supply voltage changes dynamically.
(prs) 1) Static CMOS (Complementation Logic). VDD ln :0 Vout=VDD R951?” 0%
5 Wu; lcl— l6], StdSc. 040$ opéfdﬁzs robus'l'lj 03H. varaina, VDD' \ VDD (Spec) 2) Dynamic Logic (Domino Logic). '. False, teak, low 2 AVDD > VTP  Latch of AVDD7VM/
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‘H’lal Voll—agt, Ghana}! Slop) aauak. 3. Activity Factor Calculation: Given a. switching function expression f (A, B, C) =
(A + BC + B’C’)’, we assume that all inputs toggle with a probability p1 = 0.5. (5' [7“) 1) Derive the activity factor of the output ao_>1. P0 .5; ;
f(A,»,c) = g : Z
P ' 3.  .I
MM) 23 ' ‘I—
= m = e I
l I 0
(lofts) 2) Draw one imélementation of this logic using basic gates (NOT, NOR, NAND, XOR) and compute the activity factors for all internal nodes. e X Y (.3 2
‘Xok A Z: FEEM — (A*BC*B’O" X= me ~ “MW » » <+
_ "— i. Y: x —. we 0 Misﬁt2‘; * DerUr (MWMS M (904931701, bud“ 6M1? «kc ”four baut W43 \ 1k HM— ‘h‘Pu Wm' 4. Leakage Current:  Suppose that the leakage current of a single transistor is
expressed as, 11”,, = IﬁOWakaWnﬂ/s, where A4 = 0.1 and S = 100mV. The
supply voltage V.“ = IV. The implementations of NOR2 and NOT gates are shown below.
([0 F“) 1) Calculate the voltage values VM at node M, when VA = VB = 1 in the NOR2
= Io x lo 5
s/n=l a l S l; In ““"M V /\ V
n (VH'VDD) — m + a M
\lezl ﬁlling lqulg =loxlo \S
‘ ‘ _ =\/ .. v +,\ v"
JleAk/A = 'L\¢,,k,/5 ——+ /\d (V013 VM) ‘4 DD 01
H'Ad \/ l l
—>' VM 3 ‘DD =
( +2)\oi \ 2.
(lofts) 2) Calculate the leakage ”(1110151011 ratio Ilealc.NOR/Ileal¢,N0T of N 0R2 gate compared
with the NOT gate, when VA = 1 in the NOT gate. V /\ V
V“ 0‘ TH * I M
. . I — S
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ME»: I, < Imkmo’f ——> ‘ "’ < l R 5. Parameter Variations: Digital system delay D is a function of supply voltage V.“
and threshold voltage V“ i.e. D(Vdd, V,). Let us adopt the alpha pwer law model
for transistors. Suppose the threshold voltage variata by AVt. C I‘D(NS) 1) The delay variation is limited by A7 = D(Vdd, V, + AV¢)/D(Vdd, Vt). Derive the
minimum supply voltage V“. Vdd
1%va °‘ (Void—Vt)“
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w a:  Wait) (I Vzrfwf‘
.— I V I \
.9 Vdd 2 Vt + AVt (l+ A‘CW"l) (’Olﬁsﬂ) Suppose that the supply voltage Vdd and delay variation A1 = D(Vdd.Vt +
AW)/D(Vdd, V,) are ﬁxed. Derive the limit of the threshold voltage variation AW. 71% 9am as 9H]? 0, alto/e hav¢
l W
“I = {(— jL. °<
Vald'lft 6. 6TRAM Analysis:
(4 “91) Draw the butterﬂy plot of holdmode. (Hum, 712 #Wufﬁg, put FM“
' In balanced Iv: W—modt. 45° (AL 7M WM ﬂirt «If fwdmeta [‘s 9H“ lmtamd ta w/ 9":an Low:
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TMIXW MMS 00/ BL, Va H451 oat/we (adv49M “MOS of I‘WU‘W and NMDS paCS +Y0m51§17r_
( 8 Pa) 3) Suppose the pull down nchannel transistors increase the size by twofold width.
Draw and explain the change of the plot for holdmode. mt Wok 0! b} chcmqehj 3.325 of NMOS tum I‘mlwr'ror; VTC curves Shn‘ft +04%: 617‘?
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dash MN; Prcvtbus SM (10'7“) 7. Aggressive Scaling; Describe the strategy of Razor project. For microproces
sors, the instruction replay (rollback) mechanism is builtin for prediction errors.
Describe the method to utilize the replay mechanism for aggressive voltage scaling. // Razor allows aﬂcassf/e, 554""3'“ known ’BeW—Han’woﬂsl'ﬂSC. — Camera" olbsﬁgné ﬁracf' (are, uo rsf‘ Case amouh'onS .1”, (m is G Scale, 0.le 1; (ca/er (was 34 obal wH—M
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