midterm_sol - EAL Cream(20 mel 2:0 ECE26OB/CSE241A Midterm...

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Unformatted text preview: EAL! Cream, (20 mel +2: :0 ECE26OB/CSE241A Midterm, February 16, 2010, Name Sal “Ham 1. Scaling Trend: Describe the scaling of delay, power, energy per instruction and power density according to the following models. Suppose that the technology allows three dimensional ICs, i.e. 10 dies are stacked via through silicon vias. Assume that the frequency and die size are fixed, while the voltages V44, V”, drop, the geometries of the transistor, W, L, T0,, shrink, and the number of IC dies increases with the same scaling. All scale with a factor S. L 10 (As) 1) Long channel model (a = 2 in the alpha power law model). gmifl‘lmskwr Mir”; Dgw¥rt£§ CW- VM)N°‘ (yS)N-| ,2? 01:). 12961115“ CA’ W“‘ x—é— sham mnsifiw WWWWW‘ ‘3; c We! ( —}) (4's) -1. N ___._ o( 5 Tmfm, My °‘ 1,, 5 PM” a #mmem x cvarif «(s’-9)x(-$L)(%)1v)o( m 30 any,” [.mvwh‘m o< 9W“ x Tc at U] f N PW” «x -—I- a PM A“? on mm . 5] U0 ([5) 2) Short'channel model (a = 1.2 in the alpha power law model). OIL (T (X: (.2. _ Idgtx 7‘») Cw (in—L) I 1.8 mm ...—— o< ’1’}— oz -' MN, I 3, cx as (3),”; ks) ) Trws all Power, ”my/msf'mvfimr POW dash-7' pem’f C/WW’ PW x m W7 /.hc,hu11‘w d m PM We °( LU 2. Dynamic Voltage Scaling: For dynamic voltage scaling, the supply voltage fluc- tuates according to a controlled scheduling to balance between system performance and power consumption. Describes the logic behavior of the following logic style when supply voltage changes dynamically. (prs) 1) Static CMOS (Complementation Logic). VDD ln :0 Vout=VDD R951?” 0% 5 Wu; lcl— l6], Std-Sc. 040$ opéfdfizs robus'l'lj 03H. varaina, VDD' \ VDD (Spec) 2) Dynamic Logic (Domino Logic). '. False, teak, low 2 AVDD > VTP - Latch of AVDD7VM/ *Sat; Smna‘ d per Iimi‘l' on \CLUDD/J ’3‘ Cann0‘l’ %al‘C/Cloch on a/au‘ah'on Sta *Tri-s-tafl; bu$S¢§ (2W1 magma (S‘pes) 3) Mux based Flip-Flops. use. “0' d Carma-é) FPS woald hat/e, (Jfolalfl-M- Homeroom; USMall8_a$5¢/me_ ‘H’lal- Voll—agt, Ghana}! Slop) aauak. 3. Activity Factor Calculation: Given a. switching function expression f (A, B, C) = (A + BC + B’C’)’, we assume that all inputs toggle with a probability p1 = 0.5. (5' [7“) 1) Derive the activity factor of the output ao_>1. P0 .5; ; f(A,»,c) = g : Z P ' 3. - .I MM) 23 ' ‘I— = m = e I l I 0 (lofts) 2) Draw one imélementation of this logic using basic gates (NOT, NOR, NAND, XOR) and compute the activity factors for all internal nodes. e X Y (.3 2 ‘Xok A Z: FEE-M — (A*BC*B’O" X= me ~ “MW » » <+ _ "— i. Y: x —. we 0 Misfit-2‘; * DerUr (MWMS M (904931701, bud“ 6M1? «kc ”four baut W43 \ 1k HM— ‘h‘Pu Wm' 4. Leakage Current: - Suppose that the leakage current of a single transistor is expressed as, 11”,, = IfiOWakaWnfl/s, where A4 = 0.1 and S = 100mV. The supply voltage V.“ = IV. The implementations of NOR2 and NOT gates are shown below. ([0 F“) 1) Calculate the voltage values VM at node M, when VA = VB = 1 in the NOR2 = Io x lo 5 s/n=l a l S l; In ““"M V /\ V n (VH'VDD) — m + a M \lezl filling lqulg =loxlo \S ‘ ‘ _ =\/ .. v +,\ v" JleAk/A = 'L\¢,,k,/5 ——+ /\d (V013 VM) ‘4 DD 01 H'Ad \/ l l —>' VM 3 ‘DD = ( +2)\oi \ 2. (lofts) 2) Calculate the leakage ”(1110151011 ratio Ilealc.NOR/Ileal¢,N0T of N 0R2 gate compared with the NOT gate, when VA = 1 in the NOT gate. V /\ V V“ 0‘ TH * I M . . I — S V” :l T $I|¢akly01 lat, NOT - Io K '0 ——‘4n -t A; (Vow—V94) 1 I\eal:!UoR 1° X l0 8 I k .191 -— ”Wk + )lVdcl ‘e‘ I on l0 5 A6190 ”V“ ) ‘AJ V99 7" ‘0 s -— on x Agile {—2— ——‘K—‘/‘ 4"" ~77“ ' ________._—— I\ak,wT I( a JoR ME»: I, < Imkmo’f ——> ‘ "’ < l R 5. Parameter Variations: Digital system delay D is a function of supply voltage V.“ and threshold voltage V“ i.e. D(Vdd, V,). Let us adopt the alpha pwer law model for transistors. Suppose the threshold voltage variata by AVt. C I‘D-(NS) 1) The delay variation is limited by A7 = D(Vdd, V, + AV¢)/D(Vdd, Vt). Derive the minimum supply voltage V“. Vdd 1%va °‘ (Void—Vt)“ , mu: °‘ .— ( w a: - Wait) (I- Vzrfwf‘ .— I- V I \ .9 Vdd 2 V-t + AV-t (l+ A‘CW"l) (’Olfisfl) Suppose that the supply voltage Vdd and delay variation A1 = D(Vdd.Vt + AW)/D(Vdd, V,) are fixed. Derive the limit of the threshold voltage variation AW. 71% 9am as 9H]? 0, alto/e hav¢ l W “I = {(—- jL. °< Vald'lft 6. 6T-RAM Analysis: (4 “91) Draw the butterfly plot of hold-mode. (Hum, 712 #Wuffig, put FM“ ' In balanced Iv: W—modt. 45° (AL 7M WM flirt «If fwd-meta [‘s 9H“ lmtamd ta w/ 9":an Low: (SMAUU‘ SNM) and (/TC doesnre, rue/n 0, Kasai.- TMIXW MMS 00/ BL, Va H451 oat/we (adv-49M “MOS of I‘WU‘W and NMDS paCS +Y0m51§17r_ ( 8 Pa) 3) Suppose the pull down n-channel transistors increase the size by twofold width. Draw and explain the change of the plot for hold-mode. mt Wok 0! b} chcmqehj 3.325 of NMOS tum I‘mlwr'ror; VTC curves Shn‘ft +04%: 617‘? and lnvf'om, 5141' 9H” bmfba’ l} 6a (amid -‘ WY’MfCI?) dud (ll—rho WW?” ’ pad—clown an’k (VHWW‘NMI gotta! (mm; was sat imam: dash MN; Prcvtbus SM (10'7“) 7. Aggressive Scaling; Describe the strategy of Razor project. For microproces- sors, the instruction replay (rollback) mechanism is built-in for prediction errors. Describe the method to utilize the replay mechanism for aggressive voltage scaling. // Razor allows aflcassf/e, 554""3'“ known ’BeW—Han’woflsl'flSC. — Camera" olbsfigné firacf' (are, uo rsf‘ Case amouh'onS .1”, (m is G Scale, 0.le 1; (ca/er (was 34 obal wH—M cocaiionqi errors. AT . l) Rag,“ Ermr owl—ahara: ‘* Doubly. sameb (adobe; (MM +glyadou) larch) Ade/(1‘ ~6rfaf$ - AT Add? m clock OESMdo'O lad-CL -— $649M! Lampla— K Wreck-ba-olA/Sufin " XOK 444m *2: MJ‘CCI- armp 1) 8mm GNTCCH on — Hl'croardulahoml. Suppof+2557¢5ftu3 _ . .. imina_ effo/S {7an ”£6 brand mks Infant/05:4 _ Flag/l Mala/Jae [ML/Sh” 3/ "U” Mar/ed:- mluc,‘ 3)Cha|len31/$1 mahff'AU/lmg/E 5W [MHL (grief/#9445. ...
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