Moore - NO EXPONENTIAL IS FOREVER NO Gordon E Moore Worldwide Semiconductor Revenues Worldwide $B 1000 100 10 1'68 ’70'72'74'76'78'80'82'84'86'88

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Unformatted text preview: NO EXPONENTIAL IS FOREVER . . . NO Gordon E. Moore Worldwide Semiconductor Revenues Worldwide $B 1000 100 10 1 '68 ’70 '72 '74 '76 '78 '80 '82 '84 '86 '88 ’90 '92 '94 '96 '98 '00 '02 Source: Intel/WSTS,12/02 Source Intel/WSTS,12/02 Transistors Shipped Per Year Transistors 1018 1017 1016 1015 Units 10 1013 1012 1011 1010 10 9 '68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02 14 Source: Dataquest/Intel, 12/02 Average Transistor Price By Year Average $ 10 1 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 '68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02 Source: Dataquest/Intel12/02 1” Wafer Of Planar Transistors, ~1959 1” The First Planar Integrated Circuit, 1961 The 1965 Transistor Projection 1965 Integrated Circuit Complexity Integrated Transistors Per Die 1010 109 108 107 106 105 104 103 102 101 100 1960 1965 Actual Data 1965 MOS Arrays MOS Logic 1975 Actual Data 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 Source: Intel Sour Integrated Circuit Complexity Integrated Transistors Per Die 1010 109 108 107 106 105 104 103 102 101 100 1960 1960 1965 Actual Data MOS Arrays MOS Logic 1975 Actual Data 1975 Projection 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 Source: Intel Sour Integrated Circuit Complexity Integrated Transistors Per Die 1010 109 108 107 106 105 104 103 102 101 100 1960 1965 Actual Data MOS Arrays MOS Logic 1975 Actual Data 1975 Projection Memory Microprocessor Microprocessor 256K 64K 4K 1K 4004 16K 8080 8086 80286 1M i386™ 1G 2G 256M 512M 128M Itanium™ 64M Pentium® 4 16M Pentium® III 4M Pentium® II Pentium® i486™ 4G 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 Source: Intel Sour 300mm Wafer 300mm Projected 2000 Wafer, circa 1975 Projected 57" Moore was not always accurate 90 nm Generation Interconnects 90 M7 M6 M5 Copper Interconnects M4 M3 M2 M1 Combination of copper + low-k dielectric now meeting performance and manufacturing goals Low-k CDO Dielectric Minimum Feature Size Minimum Feature Size (microns) Examples 100 ** Human hair, 100 µm Amoeba, 15 µm Red blood cell, 7 µm 10 1 Intel [update 5/20/02] ITRS [2001 edition] 0.1 AIDS virus, 0.1 µm 0.01 '60 '65 '70 '75 ’80 '85 '90 '95 ’00 Projected '05 '10 ** Planar Transistor; remaining data points are ICs. Source: Intel, post ‘96 trend data provided by SIA Sour International Technology Roadmap for Semiconductors (ITRS) Int ^ [ITRS DRAM Half-Pitch vs. Intel “Lithography”] Buckyball, 0.001 µm 1 µm2 SRAM Cell P501 Contact P501 Contact P501 1978 1978 1978 1978 P501 Contact P1262 SRAM Cell P1262 2002 2002 P1262 SRAM Cell P1262 2002 2002 1 µm 50nm Resist Lines With 193nm Light 50nm -0.2um focus -0.3um focus “best focus” +0.2um focus +0.3um focus 193nm Step and Scan Production Tool 193nm Minimum Insulator Thickness vs Time Minimum Oxide Thickness (Nanometers) 100 1.0µ 10 0.35µ 0.25µ 0.18µ 0.13µ Electrical Physical 1 '69 '7 2 '75 '7 8 '90 Source: Intel '93 '96 '99 '02 '0 5 High K for Gate Dielectrics Gate 1.2nm SiO2 Gate 3.0nm High-k Silicon substrate 90nm process Capacitance 1X Leakage 1X Source: Intel Silicon substrate Silicon Experimental high-k 1.6X < 0.01X Processor Performance (MIPS) Processor 100000 10000 1000 100 Pentium® 4 Pentium® 2 MIPS 486 Pentium® 10 1 0.1 8086 8080 386 286 8008 4004 0.01 1970 1975 1980 1985 1990 1995 2000 2005 Processor Power (Watts) - Active & Leakage Active 1000 100 Active Power (W) 10 1 0.1 0.01 Leakage 0.001 1960 1970 1980 1990 2000 2010 Processor Supply Voltage Processor 100 Power Supply (Volt) 10 1 1970 1980 1990 2000 2010 New Materials and Device Structures New Extending Transistor Scaling Changes Made Gate Silicide Added Future Options High-k Gate Dielectric New Transistor Structure Channel Strained Silicon Transistor Tri-Gate Transistor Structure Tri Lg Current WSi Drain Gate Tox Source SiO2 HSi Technology Generations to Come Technology Double the Density Reduce Line Width by 0.7x 130nm 90nm 60nm 45nm 30nm ? 90nm 60nm 45nm 30nm 2 or 3 years between generations or ~10 ± 2 Years EUV Printed and Etched Lines EUV 100 nm, k1 = 0.75 80 nm, k1 = 0.60 50 nm dense, k1 = 0.37 Extreme Ultraviolet (EUV) Lithography Extreme Lithography Tool Cost ( $ ) Lithography Exp+08 Litho Tool Cost ( $ ) Exp+07 Exp+06 Exp+05 Exp+04 1960 1970 1980 1990 2000 2010 NO EXPONENTIAL IS FOREVER . . . NO BUT WE CAN DELAY “FOREVER” ...
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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