rcwire - On-Chip Interconnect Analysis and On-Chip...

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Unformatted text preview: On-Chip Interconnect Analysis and On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Evaluation of Delay, Power, and Bandwidth Metrics under Different Bandwidth Metrics under Different Design GoalsDesign GoalsIntroductionInterconnect strategy, or interconnect planning has become a critical part of chip design:the growing significance of wire delay relative to gate delay .increasing power consumption of wires: could be up to 50% of the total dynamic power.Influences the ASIC design methodologyOur workTry to revamp the on-chip local interconnect configuration for multi-objective optimization:Compare different objective functions.Formulate various matrics to measure the wire performance.Identify the optimal wire configurations.Evaluation Approach and Modelsobjective functions:is the wire-length normalized delay.is the wire-length-normalized power....
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This note was uploaded on 03/13/2010 for the course CSE cse241a taught by Professor Cheng during the Spring '10 term at UCSD.

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rcwire - On-Chip Interconnect Analysis and On-Chip...

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