Sorin_System

Sorin_System - ECE260B CSE241A Winter 2010 Low power...

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ECE240B/CSE241A Low power techniques 1 Sorin Dobre, Qualcomm ECE260B – CSE241A Winter 2010 Low power implementation A system perspective Website: http://cseweb.ucsd.edu/classes/wi10/cse241a/
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ECE240B/CSE241A Low power techniques 2 Sorin Dobre, Qualcomm Low power implementation : Metrics User experience prospective: For mobile devices: - Active time of the device: Time interval of performing a well defined set of tasks (defined use mode: audio play , voice call, web browsing, video playback, etc ) between two battery charges - Standby time of the device: Time interval between two battery charges when the device is fully functional ready to be activated but does not perform any functional user driven tasks. For electrical powered devices: Efficiency: Power consumption for performing a defined set of tasks relative to performance metrics: - mW/Mhz Average power consumption Peak power consumption
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ECE240B/CSE241A Low power techniques 3 Sorin Dobre, Qualcomm Low power implementation : Metrics Power consumption in digital systems: P total = P active + P leakage P active = P internal + P switching = P internal + α CV²f V – voltage f – frequency C – capacitive load α – activity factor
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ECE240B/CSE241A Low power techniques 4 Sorin Dobre, Qualcomm Low power implementation: Design synergy Low power implementation in the modern system on chips today requires a holistic and concurrent approach which includes collaboration between: System level design Architectural design Software Hardware co-design IP design: - Circuit design - Physical implementation of the IP Physical design (chip/block level) Power verification and modeling Silicon correlation and validation
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ECE240B/CSE241A Low power techniques 5 Sorin Dobre, Qualcomm System optimization Power delivery network optimization: On die vs on board (PCB) voltage regulators Voltage regulators efficiency Voltage rails definition System level power management: - Adaptive voltage scaling (AVS) - Dynamic clock frequency and voltage scaling (DCVS) - Static voltage scaling (SVS) Analog vs digital processing system level optimization Optimization at the system with the goal of moving most of the signal processing (data transformation) in the digital domain. The power consumption in the digital domain is scalable with the process technology scaling and with the system use mode requirements. Digitally assisted analog processing
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Low power techniques 6 Sorin Dobre, Qualcomm Architectural optimization Memory hierarchy On die vs. off die memory Cache size (miss penalty) Cache hierarchy (architecture) Address space definition Processor architecture Von Neumann , Harvard VLIW (high IPC) 16bit, 32bit, 64 bit instruction architecture (IA) (Code compression) In order vs out of order execution Superscalar implementation Multi thread implementation Scalability : Single core vs. Multi core Application specific IA optimization - FFT cores - Multipliers, adders ,shifters
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ECE240B/CSE241A Low power techniques 7
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Sorin_System - ECE260B CSE241A Winter 2010 Low power...

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